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Freescale Semiconductor Data Sheet: Technical Data
Document Number: MC9328MX21 Rev. 3.1, 07/2006
MC9328MX21
Package Information
MC9328MX21
266 MHz
(MAPBGA-289) Ordering Information: See Table 1 on page 3
1
Introduction
Contents
1 2 3 4 5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal Descriptions . . . . . . . . . . . . . . . . . . . . 5 Specifications . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin Assignment and Package Information 95 Document Revision History . . . . . . . . . . . . 98
Freescale's i.MX family of microprocessors has demonstrated leadership in the portable handheld market. Building on the success of the MX (Media Extensions) series, the i.MX21 (MC9328MX21) provides a leap in performance with an ARM926EJ-STM microprocessor core that provides accelerated Java support in addition to highly integrated system functions. The i.MX21 device specifically addresses the needs of the smartphone and portable product markets with intelligent integrated peripherals, advanced processor core, and power management capabilities. Thei.MX21 features the advanced and power-efficient ARM926EJ-S core operating at speeds up to 266 MHz and is part of a growing family of Smart Speed products that offer high performance processing optimized for lowest power consumption. On-chip modules such as a video accelerator module, LCD controller, USB On-TheGo, 1-Wire(R) interface, CMOS sensor interface, and synchronous serial interfaces offer designers a rich suite of peripherals that can enhance many products seeking to provide a rich multimedia experience.
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. (c) Freescale Semiconductor, Inc., 2005, 2006. All rights reserved.
Introduction
For cost sensitive applications, the NAND Flash controller allows the use of low-cost NAND Flash devices to be used as primary or secondary non-volatile storage. The on-chip error correction code (ECC) and parity checking circuitry of the NAND Flash controller frees the CPU for other tasks. WLAN, Bluetooth and expansion options are provided through PCMCIA/CF, USB, and MMC/SD host controllers. The device is packaged in a 289-pin MAPBGA. System Control
JTAG/Multi ICE System Boot Clock Management
Connectivity
i.MX21
CSPI x 3 SSI x 2 I2C
ARM9 Platform Standard System I/O
Timers x 3 PWM WDOG RTC GPIO DMAC D Cache Internal Control Bus Control Memory Control ARM926EJ-S I Cache MAX MMU
Audio Mux UART x 4 1-WIRE IrDA USB OTG/ 2 Hosts
Memory Expansion
MMC/SD x 2 PCMCIA/CF
Human Interface
CSI LCD Controller SLCD Controller Keypad
Enhanced Multimedia Accelerator (eMMA)
Pre- and Post- Processing
Memory Interface
SDRAMC EIM/BMI
Video Accelerator
NFC
Figure 1. i.MX21 Functional Block Diagram
1.1
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Conventions
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET. Logic level one is a voltage that corresponds to Boolean true (1) state. Logic level zero is a voltage that corresponds to Boolean false (0) state. To set a bit or bits means to establish logic level one. To clear a bit or bits means to establish logic level zero. A signal is an electronic construct whose state conveys or changes in state convey information.
This document uses the following conventions:
MC9328MX21 Technical Data, Rev. 3.1 2 Freescale Semiconductor
Introduction
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A pin is an external physical connection. The same pin can be used to connect a number of signals. Asserted means that a discrete signal is in active logic state. -- Active low signals change from logic level one to logic level zero. -- Active high signals change from logic level zero to logic level one. Negated means that an asserted discrete signal changes logic state. -- Active low signals change from logic level zero to logic level one. -- Active high signals change from logic level one to logic level zero. LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and high bytes or words are spelled out. Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are hexadecimal.
1.2
Target Applications
The i.MX21 is targeted for advanced information appliances, smart phones, Web browsers, digital MP3 audio players, handheld computers based on the popular Palm OS platform, and messaging applications.
1.3
Reference Documentation
The following documents are required for a complete description of the i.MX21 and are necessary to design properly with the device. Especially for those not familiar with the ARM926EJ-S processor the following documents are helpful when used in conjunction with this manual.
ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100) ARM7TDMI Data Sheet (ARM Ltd., order number ARM DDI 0029) ARM920T Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C) MC9328MX21 Product Brief (order number MC9328MX21P) MC9328MX21 Reference Manual (order number MC9328MX21RM)
The Freescale manuals are available on the Freescale Semiconductor Web site at http:// www.freescale.com. These documents may be downloaded directly from the Freescale Web site, or printed versions may be ordered. The ARM Ltd. documentation is available from http://www.arm.com.
1.4
Ordering Information
Table 1. Ordering Information
Part Order Number Package Size 289-lead MAPBGA 0.65mm, 14mm x 14mm 289-lead MAPBGA 0.8mm, 17mm x 17mm 289-lead MAPBGA 0.65mm, 14mm x 14mm 289-lead MAPBGA 0.8mm, 17mm x 17mm Package Type Lead-free Lead-free Lead-free Lead-free Operating Range 0C-70C 0C-70C -30C-70C -30C-70C
Table 1 provides ordering information for the device.
MC9328MX21VK MC9328MX21VM MC9328MX21DVK MC9328MX21DVM
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 3
Introduction
Table 1. Ordering Information (Continued)
Part Order Number MC9328MX21CVK MC9328MX21CVM Package Size 289-lead MAPBGA 0.65mm, 14mm x 14mm 289-lead MAPBGA 0.8mm, 17mm x 17mm Package Type Lead-free Lead-free Operating Range -40C-85C -40C-85C
1.5
Features
The i.MX21 boasts a robust array of features that can support a wide variety of applications. Below is a brief description of i.MX21 features.
* * * ARM926EJ-S Core Complex enhanced Multimedia Accelerator (eMMA) Display and Video Modules -- LCD Controller (LCDC) -- Smart LCD Controller (SLCDC) -- CMOS Sensor Interface (CSI) Bus Master Interface (BMI) Wireless Connectivity -- Fast Infra-Red Interface (FIRI) Wired Connectivity -- USB On-The-Go (USBOTG) Controller -- Four Universal Asynchronous Receiver/Transmitters (UARTx) -- Three Configurable Serial Peripheral Interfaces (CSPIx) for High Speed Data Transfer -- Inter-IC (I2C) Bus Module -- Two Synchronous Serial Interfaces (SSI) with Inter-IC Sound (I2S) -- Digital Audio Mux -- One-Wire Controller -- Keypad Interface Memory Expansion and I/O Card Support -- Two Multimedia Card and Secure Digital (MMC/SD) Host Controller Modules Memory Interface -- External Interface Module (EIM) -- SDRAM Controller (SDRAMC) -- NAND Flash Controller (NFC) -- PCMCIA/CF Interface Standard System Resources -- Clock Generation Module (CGM) and Power Control Module -- Three General-Purpose 32-Bit Counters/Timers -- Watchdog Timer -- Real-Time Clock/Sampling Timer (RTC) -- Pulse-Width Modulator (PWM) Module -- Direct Memory Access Controller (DMAC) -- General-Purpose I/O (GPIO) Ports -- Debug Capability
MC9328MX21 Technical Data, Rev. 3.1 4 Freescale Semiconductor
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Signal Descriptions
2
Signal Descriptions
Table 2 identifies and describes the i.MX21 signals. Pin assignment is provided in Section 4, "Pin Assignment and Package Information" and in the "Signal Multiplexing Scheme" table within the reference manual. The connections of the pins in Table 2 depends solely upon the user application, however there are a few factory test signals that are not used in a normal application. Following is a list of these signals and how they are to be terminated for proper operation of the i.MX21 processor: * CLKMODE[1:0]: To ensure proper operation, leave these signals as no connects. * OSC26M_TEST: To ensure proper operation, leave this signal as no connect. * EXT_48M: To ensure proper operation, connect this signal to ground. * EXT_266M: To ensure proper operation, connect this signal to ground. * TEST_WB[2:0]: These signals are also multiplexed with GPIO PORT E as well as alternate keypad signals. If not utilizing these signals for GPIO functionality or for their other multiplexed function, then configure as GPIO input with pull up enabled, and leave as a no connect. * TEST_WB[4:3]: To ensure proper operation, leave these signals as no connects.
Table 2. i.MX21 Signal Descriptions
Signal Name Function/Notes External Bus/Chip Select (EIM) A [25:0] D [31:0] EB0 EB1 EB2 EB3 OE CS [5:0] Address bus signals Data bus signals MSB Byte Strobe--Active low external enable byte signal that controls D [31:24], shared with SDRAM DQM0. Byte Strobe--Active low external enable byte signal that controls D [23:16], shared with SDRAM DQM1. Byte Strobe--Active low external enable byte signal that controls D [15:8], shared with SDRAM DQM2 and PCMCIA PC_REG. LSB Byte Strobe--Active low external enable byte signal that controls D [7:0], shared with SDRAM DQM3 and PCMCIA PC_IORD. Memory Output Enable--Active low output enables external data bus, shared with PCMCIA PC_IOWR. Chip Select--The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the Function Multiplexing Control Register (FMCR) in the System Control chapter. By default CSD [1:0] is selected. DTACK is multiplexed with CS4. Active low input signal sent by flash device to the EIM whenever the flash device must terminate an ongoing burst sequence and initiate a new (long first access) burst sequence. Active low signal sent by flash device causing the external burst device to latch the starting burst address. Clock signal sent to external synchronous memories (such as burst flash) during burst mode. RW signal--Indicates whether external access is a read (high) or write (low) cycle. This signal is also shared with the PCMCIA PC_WE. DTACK signal--External input data acknowledge signal, multiplexed with CS4.
ECB LBA BCLK RW DTACK
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 5
Signal Descriptions
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name Function/Notes Bootstrap BOOT [3:0] System Boot Mode Select--The operational system boot mode upon system reset is determined by the settings of these pins. To hardwire these inputs low, terminate with a 1 K resister to ground. For a logic high, terminate with a 1 K resistor to VDDA. Do not change the state of these inputs after power-up. Boot 3 should always be tied to logic low. SDRAM Controller SDBA [4:0] SDIBA [3:0] MA [11:0] DQM [3:0] CSD0 CSD1 RAS CAS SDWE SDCKE0 SDCKE1 SDCLK SDRAM non-interleave mode bank address signals. These signals are multiplexed with address signals A[20:16]. SDRAM interleave addressing mode bank address signals. These signals are multiplexed with address signals A[24:21]. SDRAM address signals. MA[9:0] are multiplexed with address signals A[10:1]. SDRAM data qualifier mask multiplexed with EB[3:0]. DQM3 corresponds to D[31:24], DQM2 corresponds to D[23:16], DQM1 corresponds to D[15:8], and DQM0 corresponds to D[7:0]. SDRAM Chip Select signal. This signal is multiplexed with the CS2 signal. This signal is selectable by programming the Function Multiplexing Control Register in the System Control chapter. SDRAM Chip Select signal. This signal is multiplexed with the CS3 signal. This signal is selectable by programming the Function Multiplexing Control Register in the System Control chapter. SDRAM Row Address Select signal. SDRAM Column Address Select signal SDRAM Write Enable signal SDRAM Clock Enable 0 SDRAM Clock Enable 1 SDRAM Clock Clocks and Resets EXTAL26M Crystal input (26MHz), or a 16 MHz to 32 MHz oscillator (or square-wave) input when the internal oscillator circuit is shut down. When using an external signal source, feed this input with a square wave signal switching from GND to VDDA. Oscillator output to external crystal. When using an external signal source, float this output. 32 kHz or 32.768 kHz crystal input. When using an external signal source, feed this input with a square wave signal switching from GND to QVDD5. Oscillator output to external crystal. When using an external signal source, float this output. Clock Out signal selected from internal clock signals. Please refer to clock controller for internal clock selection. This is a special factory test signal. To ensure proper operation, connect this signal to ground. This is a special factory test signal. To ensure proper operation, connect this signal to ground. Master Reset--External active low Schmitt trigger input signal. When this signal goes active, all modules (except the reset module, SDRAMC module, and the clock control module) are reset. Reset Out--Internal active low output signal from the Watchdog Timer module and is asserted from the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out. Power On Reset--Active low Schmitt trigger input signal. The POR signal is normally generated by an external RC circuit designed to detect a power-up event.
XTAL26M EXTAL32K XTAL32K CLKO EXT_48M EXT_266M RESET_IN RESET_OUT POR
MC9328MX21 Technical Data, Rev. 3.1 6 Freescale Semiconductor
Signal Descriptions
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name CLKMODE[1:0] OSC26M_TEST TEST_WB[2:0] Function/Notes These are special factory test signals. To ensure proper operation, leave these signals as no connects. This is a special factory test signal. To ensure proper operation, leave this signal as a no connect. These are special factory test signals. However, these signals are also multiplexed with GPIO PORT E as well as alternate keypad signals. If not using these signals for GPIO functions or for other multiplexed functions, then configure as GPIO input with pull-up enabled, and leave as a no connect. These are special factory test signals. To ensure proper operation, leave these signals as no connects. Battery indicator input used to qualify the walk-up process. Also multiplexed with TIN.
TEST_WB[4:3] WKGD
JTAG For termination recommendations, see the Table "JTAG pinouts" in the Multi-ICE(R) User Guide from ARM(R) Limited. TRST TDO TDI TCK TMS JTAG_CTRL Test Reset Pin--External active low signal used to asynchronously initialize the JTAG controller. Serial Output for test instructions and data. Changes on the falling edge of TCK. Serial Input for test instructions and data. Sampled on the rising edge of TCK. Test Clock to synchronize test logic and control register access through the JTAG port. Test Mode Select to sequence the JTAG test controller's state machine. Sampled on the rising edge of TCK. JTAG Controller select signal--JTAG_CTRL is sampled during the rising edge of TRST. Must be pulled to logic high for proper JTAG interface to debugger. Pulling JTAG_CRTL low is for internal test purposes only. JTAG Return Clock used to enhance stability of JTAG debug interface devices. This signal is multiplexed with 1-Wire, therefore using 1-Wire renders RTCK unusable and vice versa. CMOS Sensor Interface CSI_D [7:0] CSI_MCLK CSI_VSYNC CSI_HSYNC CSI_PIXCLK Sensor port data Sensor port master clock Sensor port vertical sync Sensor port horizontal sync Sensor port data latch clock LCD Controller LD [17:0] LCD Data Bus--All LCD signals are driven low after reset and when LCD is off. LD[15:0] signals are multiplexed with SLCDC1_DAT[15:0] from SLCDC1 and BMI_D[15:0]. LD[17] signal is multiplexed with BMI_WRITE of BMI. LD[16] is multiplexed with BMI_READ_REQ of BMI and EXT_DMAGRANT. Frame Sync or Vsync--This signal also serves as the clock signal output for gate driver (dedicated signal SPS for Sharp panel HR-TFT). This signal is multiplexed with BMI_RXF_FULL and BMI_WAIT of the BMI.
RTCK
FLM_VSYNC (or simply referred to as VSYNC)
LP_HSYNC (or simply Line Pulse or HSync referred to as HSYNC) LSCLK OE_ACD CONTRAST SPL_SPR Shift Clock. This signal is multiplexed with the BMI_CLK_CS from BMI. Alternate Crystal Direction/Output Enable. This signal is used to control the LCD bias voltage as contrast control. This signal is multiplexed with the BMI_READ from BMI. Sampling start signal for left and right scanning. This signal is multiplexed with the SLCDC1_CLK.
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 7
Signal Descriptions
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name PS CLS REV Function/Notes Control signal output for source driver (Sharp panel dedicated signal). This signal is multiplexed with the SLCDC1_CS. Start signal output for gate driver. This signal is invert version of PS (Sharp panel dedicated signal). This signal is multiplexed with the SLCDC1_RS. Signal for common electrode driving signal preparation (Sharp panel dedicated signal). This signal is multiplexed with SLCDC1_D0. Smart LCD Controller SLCDC1_CLK SLCDC1_CS SLCDC1_RS SLCDC1_D0 SLCDC Clock output signal. This signal is multiplexed and available at 2 alternate locations. These are SPL_SPR and SD2_CLK signals of LCDC and SD2, respectively. SLCDC Chip Select output signal. This signal is multiplexed and available at 2 alternate signal locations. These are PS and SD2_CMD signals of LCDC and SD2, respectively. SLCDC Register Select output signal. This signal is multiplexed and available at 2 alternate signal locations. These are CLS and SD2_D3 signals of LCDC and SD2, respectively. SLCDC serial data output signal. This signal is multiplexed and available at 2 alternate signal locations. These are and REV and SD2_D2 signals of LCDC and SD2, respectively. This signal is inactive when a parallel data interface is used. SLCDC Data output signals for connection to a parallel SLCD panel interface. These signals are multiplexed with LD[15:0] while an alternate 8-bit SLCD muxing is available on LD[15:8]. Further alternate muxing of these signals are available on some of the USB OTG and USBH1 signals. SLCDC Clock input signal for pass through to SLCD device. This signal is multiplexed with SSI3_CLK signal from SSI3. SLCDC Chip Select input signal for pass through to SLCD device. This signal is multiplexed with SSI3_TXD signal from SSI3. SLCDC Register Select input signal for pass through to SLCD device. This signal is multiplexed with SSI3_RXD signal from SSI3. SLCD Data input signal for pass through to SLCD device. This signal is multiplexed with SSI3_FS signal from SSI3. Bus Master Interface (BMI) BMI_D[15:0] BMI_CLK_CS BMI_WRITE BMI bidirectional data bus. Bus width is programmable between 8-bit or 16-bit.These signals are multiplexed with LD[15:0] and SLCDC_DAT[15:0]. BMI bidirectional clock or chip select signal.This signal is multiplexed with LSCLK of LCDC. BMI bidirectional signal to indicate read or write access. This is an input signal when the BMI is a slave and an output signal when BMI is the master of the interface. BMI_WRITE is asserted for write and negated for read.This signal is muxed with LD[17] of LCDC. BMI output signal to enable data read from external slave device. This signal is not used and driven high when BMI is slave.This signal is multiplexed with CONTRAST signal of LCDC. BMI Read request output signal to external bus master. This signal is active when the data in the TXFIFO is larger or equal to the data transfer size of a single external BMI access.This signal is muxed with LD[16] of LCDC. BMI Receive FIFO full active high output signal to reflect if the RxFIFO reaches water mark value.This signal is muxed with VSYNC of the LCDC. BMI Wait--Active low signal to wait for data ready (read cycle) or accepted (write_cycle). Also multiplexed with VSYNC.
SLCDC1_DAT[15:0]
SLCDC2_CLK SLCDC2_CS SLCDC2_RS SLCDC2_D0
BMI_READ BMI_READ_REQ
BMI_RXF_FULL BMI_WAIT
MC9328MX21 Technical Data, Rev. 3.1 8 Freescale Semiconductor
Signal Descriptions
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name Function/Notes External DMA EXT_DMAREQ EXT_DMAGRANT External DMA Request input signal. This signal is multiplexed with CSPI1_RDY. External DMA Grant output signal. This signal is multiplexed with LD[16] of LCDC and CSPI1_SS1 of CSPI1. NAND Flash Controller NF_CLE NF_CE NF_WP NF_ALE NF_RE NF_WE NF_RB NF_IO[15:0] NAND Flash Command Latch Enable output signal. Multiplexed with PC_POE of PCMCIA. NAND Flash Chip Enable output signal. This signal is multiplexed with PC_CE1 of PCMCIA. NAND Flash Write Protect output signal. This signal is multiplexed with PC_CE2 of PCMCIA. NAND Flash Address Latch Enable output signal. This signal is multiplexed with PC_OE of PCMCIA. NAND Flash Read Enable output signal. This signal is multiplexed with PC_RW of PCMCIA. NAND Flash Write Enable output signal. This signal is multiplexed with and PC_BVD2 of PCMCIA. NAND Flash Ready Busy input signal. This signal is multiplexed with PC_RST of PCMCIA. NAND Flash Data input and output signals. NF_IO[15:7] signals are multiplexed with A[25:21] and A[15:13]. NF_IO[7:0] signals are multiplexed with several PCMCIA signals. PCMCIA Controller PC_A[25:0] PC_D[15:0] PC_CD1 PC_CD2 PC_WAIT PC_READY PC_RST PC_OE PC_WE PC_VS1 PC_VS2 PC_BVD1 PC_BVD2 PC_SPKOUT PC_REG PC_CE1 PC_CE2 PC_IORD PC_IOWR PC_WP PCMCIA Address signals. These signals are multiplexed with A[25:0]. PCMCIA Data input and output signals. These signals are multiplexed with D[15:0]. PCMCIA Card Detect1 input signal. This signal is multiplexed with NFIO[7] signal of NF. PCMCIA Card Detect2 input signal. This signal is multiplexed with NFIO[6] signal of NF. PCMCIA Wait input signal to extend current access. This signal is multiplexed with NFIO[5] signal of NF. PCMCIA Ready input signal indicates card is ready for access. Multiplexed with NFIO[4] signal of NF. PCMCIA Reset output signal. This signal is multiplexed with NFRB signal of NF. PCMCIA Memory Read Enable output signal asserted during common or attribute memory read cycles. This signal is multiplexed with NFALE signal of NF. PCMCIA Memory Write Enable output signal asserted during common or attribute memory cycles. This signal is shared with RW of the EIM. PCMCIA Voltage Sense1 input signal. This signal is multiplexed with NFIO[2] signal of NF. PCMCIA Voltage Sense2 input signal. This signal is multiplexed with NFIO[1] signal of NF. PCMCIA Battery Voltage Detect1 input signal. This signal is multiplexed with NFIO[0] signal of NF. PCMCIA Battery Voltage Detect2 input signal. This signal is multiplexed with NF_WE signal of NF. PCMCIA Speaker Out output signal. This signal is multiplexed with PWMO signal. PCMCIA Register Select output signal. This signal is shared with EB2 of EIM. PCMCIA Card Enable1 output signal. This signal is multiplexed with NFCE signal of NF. PCMCIA Card Enable2 output signal. This signal is multiplexed with NFWP signal of NF. PCMCIA IO Read output signal. This signal is shared with EB3 of EIM. PCMCIA IO Write output signal. This signal is shared with OE signal of EIM. PCMCIA Write Protect input signal. This signal is multiplexed with NFIO[3] signal of NF.
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 9
Signal Descriptions
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name PC_POE PC_RW PC_PWRON Function/Notes PCMCIA Output Enable signal to enable voltage translation buffers and transceivers. This signal is multiplexed with NFCLE signal of NF. PCMCIA Read Write output signal to control external transceiver direction. Asserted high for read access and negated low for write access. This signal is multiplexed with NFRE signal of NF. PCMCIA input signal to indicate that the card power has been applied and stabilized. CSPI CSPI1_MOSI CSPI1_MISO CSPI1_SS[2:0] CSPI1_SCLK CSPI1_RDY CSPI2_MOSI CSPI2_MISO CSPI2_SS[2:0] CSPI2_SCLK CSPI3_MOSI CSPI3_MISO CSPI3_SS CSPI3_SCLK Master Out/Slave In signal Master In/Slave Out signal Slave Select (Selectable polarity) signal. CSPI1_SS2 is also multiplexed with USBG_RXDAT and CSPI1_SS1 is multiplexed with EXT_DMAGRANT. Serial Clock signal Serial Data Ready signal. Also multiplexed with EXT_DMAREQ. Master Out/Slave In signal. This signal is multiplexed with USBH2_TXDP signal of USB OTG. Master In/Slave Out signal. This signal is multiplexed with USBH2_TXDM signal of USB OTG. Slave Select (Selectable polarity) signals. These signals are multiplexed with USBH2_FS, USBH2_RXDP and USBH2_RXDM signal of USB OTG Serial Clock signal. This signal is multiplexed with USBH2_OE signal of USB OTG Master Out/Slave In signal. This signal is multiplexed with SD1_CMD. Master In/Slave Out signal. This signal is multiplexed with SD1_D0. Slave Select (Selectable polarity) signal multiplexed with SD1_D3. Serial Clock signal. This signal is multiplexed with SD1_CLK. General Purpose Timers TIN Timer Input Capture or Timer Input Clock--The signal on this input is applied to all 3 timers simultaneously. This signal is muxed with the Walk-up Guard Mode WKGD signal in the PLL, Clock, and Reset Controller module. Timer Output signal from General Purpose Timer1 (GPT1). This signal is multiplexed with SYS_CLK1 and SYS_CLK2 signal of SSI1 and SSI2. The pin name of this signal is simply TOUT. Timer Output signal from General Purpose Timer1 (GPT2). This signal is multiplexed with PWMO. Timer Output signal from General Purpose Timer1 (GPT3). This signal is multiplexed with PWMO. USB On-The-Go USB_BYP USB_PWR USB_OC USBG_RXDP USBG_RXDM USBG_TXDP USBG_TXDM USBG_RXDAT USB Bypass input active low signal. This signal can only be used for USB function, not for GPIO. USB Power output signal USB Over current input signal. This signal can only be used for USB function, not for GPIO. USB OTG Receive Data Plus input signal. This signal is muxed with SLCDC1_DAT15. USB OTG Receive Data Minus input signal. This signal is muxed with SLCDC1_DAT14. USB OTG Transmit Data Plus output signal. This signal is muxed with SLCDC1_DAT13. USB OTG Transmit Data Minus output signal. This signal is muxed with SLCDC1_DAT12. USB OTG Transceiver differential data receive signal. Multiplexed with CSPI1_SS2.
TOUT1 (or simply TOUT) TOUT2 TOUT3
MC9328MX21 Technical Data, Rev. 3.1 10 Freescale Semiconductor
Signal Descriptions
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name USBG_OE USBG_ON USBG_FS USBH1_RXDP Function/Notes USB OTG Output Enable signal. This signal is muxed with SLCDC1_DAT11. USB OTG Transceiver ON output signal. This signal is muxed with SLCDC1_DAT9. USB OTG Full Speed output signal. This signal is multiplexed with external transceiver USBG_TXR_INT signal of USB OTG. This signal is muxed with SLCDC1_DAT10. USB Host1 Receive Data Plus input signal. This signal is multiplexed with UART4_RXD and SLCDC1_DAT6. It also provides an alternative multiplex for UART4_RTS, where this signal is selectable by programming the Function Multiplexing Control Register in the System Control chapter. USB Host1 Receive Data Minus input signal. This signal is muxed with SLCDC1_DAT5. It also provides an alternative multiplex for UART4_CTS. USB Host1 Transmit Data Plus output signal. This signal is multiplexed with UART4_CTS and SLCDC1_DAT4. It also provides an alternative multiplex for UART4_RXD, where this signal is selectable by programming the Function Multiplexing Control Register in the System Control chapter. USB Host1 Transmit Data Minus output signal. Multiplexed with UART4_TXD and SLCDC1_DAT3. USB Host1 Transceiver differential data receive signal. Multiplexed with USBH1_FS. USB Host1 Output Enable signal. This signal is muxed with SLCDC1_DAT2. USB Host1 Full Speed output signal. Multiplexed with UART4_RTS and SLCDC1_DAT1 and USBH1_RXDAT. USB Host transceiver ON output signal. This signal is muxed with SLCDC1_DAT0. USB Host2 Receive Data Plus input signal. This signal is multiplexed with CSPI2_SS[1] of CSPI2. USB Host2 Receive Data Minus input signal. This signal is multiplexed with CSPI2_SS[2] of CSPI2. USB Host2 Transmit Data Plus output signal. This signal is multiplexed with CSPI2_MOSI of CSPI2. USB Host2 Transmit Data Minus output signal. This signal is multiplexed with CSPI2_MISO of CSPI2. USB Host2 Output Enable signal. This signal is multiplexed with CSPI2_SCLK of CSPI2. USB Host2 Full Speed output signal. This signal is multiplexed with CSPI2_SS[0] of CSPI2. USB OTG I2C Clock input/output signal. This signal is multiplexed with SLCDC1_DAT8. USB OTG I2C Data input/output signal. This signal is multiplexed with SLCDC1_DAT7. USB OTG transceiver interrupt input. Multiplexed with USBG_FS. Secure Digital Interface SD1_CMD SD Command bidirectional signal--If the system designer does not want to make use of the internal pullup, via the Pull-up enable register, a 4.7k-69k external pull-up resistor must be added. This signal is multiplexed with CSPI3_MOSI. SD Output Clock. This signal is multiplexed with CSPI3_SCLK. SD Data bidirectional signals--If the system designer does not want to make use of the internal pull-up, via the Pull-up enable register, a 50k-69k external pull-up resistor must be added. SD1_D[3] is muxed with CSPI3_SS while SD1_D[0] is muxed with CSPI3_MISO. SD Command bidirectional signal. This signal is multiplexed with SLCDC1_CS signal from SLCDC1. SD Output Clock signal. This signal is multiplexed with SLCDC1_CLK signal from SLCDC1. SD Data bidirectional signals. SD2_D[3:2] are multiplexed with SLCDC1_RS and SLCDC_D0 signals from SLCDC1.
USBH1_RXDM USBH1_TXDP
USBH1_TXDM USBH1_RXDAT USBH1_OE USBH1_FS USBH_ON USBH2_RXDP USBH2_RXDM USBH2_TXDP USBH2_TXDM USBH2_OE USBH2_FS USBG_SCL USBG_SDA USBG_TXR_INT
SD1_CLK SD1_D[3:0]
SD2_CMD SD2_CLK SD2_D[3:0]
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 11
Signal Descriptions
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name Function/Notes UARTs - IrDA/Auto-Bauding UART1_RXD UART1_TXD UART1_RTS UART1_CTS UART2_RXD UART2_TXD UART2_RTS UART2_CTS UART3_RXD UART3_TXD UART3_RTS UART3_CTS UART4_RXD UART4_TXD UART4_RTS UART4_CTS Receive Data input signal Transmit Data output signal Request to Send input signal Clear to Send output signal Receive Data input signal. This signal is multiplexed with KP_ROW6 signal from KPP. Transmit Data output signal. This signal is multiplexed with KP_COL6 signal from KPP. Request to Send input signal. This signal is multiplexed with KP_ROW7 signal from KPP. Clear to Send output signal. This signal is multiplexed with KP_COL7 signal from KPP. Receive Data input signal. This signal is multiplexed with IR_RXD from FIRI. Transmit Data output signal. This signal is multiplexed with IR_TXD from FIRI. Request to Send input signal Clear to Send output signal Receive Data input signal which is multiplexed with USBH1_RXDP and USBH1_TXDP. Transmit Data output signal which is multiplexed with USBH1_TXDM. Request to Send input signal which is multiplexed with USBH1_FS and USBH1_RXDP. Clear to Send output signal which is multiplexed with USBH1_TXDP and USBH1_RXDM. Serial Audio Port - SSI (configurable to I2S protocol and AC97) SSI1_CLK SSI1_TXD SSI1_RXD SSI1_FS SYS_CLK1 SSI2_CLK SSI2_TXD SSI2_RXD SSI2_FS SYS_CLK2 SSI3_CLK SSI3_TXD SSI3_RXD SSI3_FS SAP_CLK SAP_TXD SAP_RXD SAP_FS Serial clock signal which is output in master or input in slave Transmit serial data Receive serial data Frame Sync signal which is output in master and input in slave SSI1 master clock. Multiplexed with TOUT. Serial clock signal which is output in master or input in slave. Transmit serial data signal Receive serial data Frame Sync signal which is output in master and input in slave. SSI2 master clock. Multiplexed with TOUT. Serial clock signal which is output in master or input in slave. Multiplexed with SLCDC2_CLK Transmit serial data signal which is multiplexed with SLCDC2_CS Receive serial data which is multiplexed with SLCDC2_RS Frame Sync signal which is output in master and input in slave. Multiplexed with SLCDC2_D0. Serial clock signal which is output in master or input in slave. Transmit serial data Receive serial data Frame Sync signal which is output in master and input in slave.
MC9328MX21 Technical Data, Rev. 3.1 12 Freescale Semiconductor
Signal Descriptions
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name I2C I2C_CLK I2C_DATA I2C Clock I2C Data 1-Wire OWIRE 1-Wire input and output signal. This signal is multiplexed with JTAG RTCK. PWM PWMO PWM Output. This signal is multiplexed with PC_SPKOUT of PCMCIA, as well as TOUT2 and TOUT3 of the General Purpose Timer module. General Purpose Input/Output PF[16] Dedicated GPIO. When unused, program this signal as an input with the on-chip pull-up resistor enabled. Keypad KP_COL[7:0] Keypad Column selection signals. KP_COL[7:6] are multiplexed with UART2_CTS and UART2_TXD respectively. Alternatively, KP_COL6 is also available on the internal factory test signal TEST_WB2. The Function Multiplexing Control Register in the System Control chapter must be used in conjunction with programming the GPIO multiplexing (to select the alternate signal multiplexing) to choose which signal KP_COL6 is available. Keypad Row selection signals. KP_ROW[7:6] are multiplexed with UART2_RTS and UART2_RXD signals respectively. Alternatively, KP_ROW7 and KP_ROW6 are available on the internal factory test signals TEST_WB0 and TEST_WB1 respectively. The Function Multiplexing Control Register in the System Control chapter must be used in conjunction with programming the GPIO multiplexing (to select the alternate signal multiplexing) to choose which signals KP_ROW6 and KP_ROW7 are available. Noisy Supply Pins NVDD NVSS Noisy Supply for the I/O pins. There are six (6) I/O voltages, NVDD1 through NVDD6. Noisy Ground for the I/O pins Supply Pins - Analog Modules VDDA QVSS (internally connected to AVSS) Supply for analog blocks Quiet GND for analog blocks (QVSS and AVSS are synonymous) Internal Power Supplies QVDD QVSS QVDDX Power supply pins for silicon internal circuitry Quiet GND pins for silicon internal circuitry Power supply pin for the ARM core. Externally connect directly to QVDD Function/Notes
KP_ROW[7:0]
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 13
Specifications
3
3.1
Specifications
Maximum Ratings
CAUTION Stresses beyond those listed under "Maximum Ratings," (Table 3) may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under "266 MHz Recommended Operating Range" (Table 4) is not implied. Exposure to maximum-rated conditions for extended periods may affect device reliability.
Table 3. Maximum Ratings
This section contains the electrical specifications and timing diagrams for the i.MX21 processor.
Table 3 provides the maximum ratings.
Ref. Num 1 Supply Voltage
Parameter
Symbol QVDDmax, QVDDXmax NVDDmax, VDDAmax VImax Tstorage
Min -0.3 -0.3 -0.3 -55
Max 2.1 3.3 VDD + 0.31
Units V V V
oC
2 3
Input Voltage Range Storage Temperature Range
150
1. VDD is the supply voltage associated with the input. See Signal Multiplexing Scheme table in the reference manual.
3.2
Recommended Operating Range
Table 4 provides the recommended operating ranges. The device has multiple pairs of VDD and VSS power supply and return pins. QVDD, QVDDx, and QVSS pins are used for internal logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of VDD and VSS provides power to the enclosed I/O pads. This design allows different peripheral supply voltage levels in a system. Because VDDA pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter the VDDA pins from other VDD pins. For more information about I/O pads grouping per VDD, please refer to Table 4.
Table 4. 266 MHz Recommended Operating Range
Rating Operating temperature range Part No. Suffix VK, VM DVK, DVM CVK, CVM I/O supply voltage NVDD 1-6 Internal supply voltage (Core = 266 MHz) Analog supply voltage TA TA TA NVDDx QVDD, QVDDx VDDA 0 -30 - 40 1.70 1.45 1.70 70 70 85 3.30 1.65 3.30 C C C V V V Symbol Minimum Maximum Unit
MC9328MX21 Technical Data, Rev. 3.1 14 Freescale Semiconductor
Specifications
3.3
DC Electrical Characteristics
Table 5. DC Characteristics
Parameter Symbol VIH VIL VOH VOL IOH_S Test Conditions - - IOH = spec'ed Drive IOL = spec'ed Drive Vout=0.8NVDD DSCR2 = 000 DSCR = 001 DSCR = 011 DSCR = 111 Vout=0.8NVDD1 DSCR2 = 000 DSCR = 001 DSCR = 011 DSCR = 111 Vout=0.2NVDD DSCR2 = 000 DSCR = 001 DSCR = 011 DSCR = 111 Vout=0.2NVDD1 DSCR2 = 000 DSCR = 001 DSCR = 011 DSCR = 111 - Min 0.7NVDD O 0.8NVDD - -2 -4 -8 -12 - -3.5 -4.5 -5.5 -6.5 - 2 4 8 12 - 3.5 4.5 5.5 6.5 - 0.75 - Vin = 0 or NVDD VI/O = NVDD or 0 I/O = High impedance state - - - - - 0.3 - - 2.15 - - 1 5 V V V A A - mA - mA - mA Typ1 - - - - - Max NVDD 0.3NVDD - 0.2NVDD - V V mA Units
Table 5 contains the DC characteristics of the i.MX21.
High-level input voltage Low-level Input voltage High-level output voltage Low-level output voltage High-level output current, slow I/O
High-level output current, fast I/O
IOH_F
Low-level output current, slow I/O
IOL_S
Low-level output current, fast I/O
IOL_F
Schmitt trigger Positive-input threshold Schmitt trigger Negative-input threshold Hysteresis Input leakage current (no pull-up or pulldown) I/O leakage current
VT + VT VHYS Iin IOZ
1. Data labeled Typical is not guaranteed, but is intended as an indication of the IC's potential performance. 2. For DSCR definition refer to the System Control chapter in the reference manual.
Table 6 shows the input and output capacitance for the device.
Table 6. Input/Output Capacitance
Parameter Input capacitance Output capacitance Symbol Ci Co Min
- -
Typ
- -
Max 5 5
Units pF pF
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 15
Specifications
Table 7 shows the power consumption for the device.
Table 7. Power Consumption
ID 1 Parameter Run Current Conditions QVDD = QVDDX = 1.65V, NVDD1 = 1.8V. NVDD2 through NVDD6 = VDDA = 3.1V. Core = 266 MHz, System = 133 MHz. MPEG4 Playback (QVGA) from MMC/SD card, 30fps, 44.1kHz audio. Symbol IQVDD + IQVDDX INVDD1 INVDD2 through INVDD6 + IVDDA ISTBY QVDD = QVDDX = 1.65V, TA1 QVDD = QVDDX = 1.65V, 25 QVDD = QVDDX = 1.55V, 25 - - 320 1800 700 - A A A Typ Max Units 120 8 6.6 - - - mA mA mA
2
Sleep Current Standby current with Well Biasing System enabled. Well Bias Control Register (WBCR) must be set as follows: WBCR: CRM_WBS bits = 01 CRM_WBFA bit = 1 CRM_WBM bits = 001 CRM_SPA_SEL bit = 1 FMCR bit = 1 For WBCR definition refer to System Control Chapter in the reference manual.
1. TA = 70C for suffixes VK, VM, DVK, DVM, and SVK. TA = 85C for suffixes CVK, CVM, and SCVK.
3.4
AC Electrical Characteristics
The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All signals are specified relative to an appropriate edge of other signals. All timing specifications are specified at a system operating frequency (HCLK) from 0 MHz to 133 MHz (core operating frequency 266 MHz) with an operating supply voltage from VDD min to VDD max under an operating temperature from TL to TH. All timing is measured at 30 pF loading with the exception of fast I/O signals as discussed below. Refer to the reference manual's System Control Chapter for details on drive strength settings. Table 8 provides the maximum loading guidelines that can be tolerated on a memory I/O signal (also known as Fast I/O) to achieve 133 MHz operation. These critical signals include the SDRAM Clock (SDCLK), Data Bus signals (D[31:0]), lower order address signals such as A0-A10, MA10, MA11, and other signals required to meet 133 MHz timing. The values shown in Table 8 apply over the recommended operating temperature range. Care must be taken to minimize parasitic capacitance of associated printed circuit board traces.
Table 8. Loading Guidelines for Fast IO Signals to Achieve 133MHz Operation
Drive Strength Setting (DSCR2-DSCR12) 000: 3.5 mA 001: 4.5 mA 011: 5.5 mA 111: 6.5 mA Maximum I/O Loading at 1.8V 9 pF 12 pF 15 pF 19 pF Maximum I/O Loading at 3.0V 12 pF 16 pF 21 pF 26 pF
MC9328MX21 Technical Data, Rev. 3.1 16 Freescale Semiconductor
Specifications
Table 9. 32k/26M Oscillator Signal Timing
Parameter EXTAL32k input jitter (peak to peak) for both System PLL and MCUPLL EXTAL32k input jitter (peak to peak) for MCUPLL only EXTAL32k startup time Minimum - - 800 RMS 5 5 - Maximum 20 100 - Unit ns ns ms
Table 10. CLKO Rise/Fall Time (at 30pF Loaded)
Best Case Rise Time Fall Time 0.80 0.74 Typical 1.00 1.08 Worst Case 1.40 1.67 Units ns ns
3.5
DPLL Timing Specifications
Parameters of the DPLL are given in Table 11. In this table, Tref is a reference clock period after the predivider and Tdck is the output double clock period.
Table 11. DPLL Specifications
Parameter Reference clock frequency range Pre-divider output clock frequency range Double clock frequency range Pre-divider factor (PD) Total multiplication factor (MF) MF integer part MF numerator MF denominator Frequency lock-in time after full reset Frequency lock-in time after partial reset Phase lock-in time after full reset Phase lock-in time after partial reset Frequency jitter (p-p) Phase jitter (p-p) Power dissipation Vcc = 1.5V Vcc = 1.5V Vcc = 1.5V - Includes both integer and fractional parts - Should be less than the denominator - FOL mode for non-integer MF (does not include pre-multi lock-in time) FOL mode for non-integer MF (does not include pre-multi lock-in time) FPL mode and integer MF (does not include pre-multi lock-in time) FPL mode and integer MF (does not include pre-multi lock-in time) - Integer MF, FPL mode, Vcc=1.7V FOL mode, integer MF, fdck = 560 MHz, Vcc = 1.5V Test Conditions Minimum 16 16 220 1 5 5 0 1 350 220 480 360 - - - Typical - - - - - - - - 400 280 530 410 0.02 1.0 1.5 Maximum 320 32 560 16 15 15 1022 1023 450 330 580 460 0.03 1.5 - Unit MHz MHz MHz - - - - - Tref Tref Tref Tref 2*Tdck ns mW (Avg)
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 17
Specifications
3.6
Reset Module
The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 2 and Figure 3. Be aware that NVDD must ramp up to at least 1.7V for NVDD1 and 2.7V for NVDD2-6 before QVDD is powered up to prevent forward biasing.
POR
1 Can be adjusted depending on the crystal start-up time 32kHz or 32.768kHz 2
RESET_POR Exact 300ms RESET_DRAM 4 HRESET RESET_OUT 3 7 cycles @ CLK32
14 cycles @ CLK32
CLK32
HCLK
Figure 2. Timing Relationship with POR
5 RESET_IN
14 cycles @ CLK32
HRESET
RESET_OUT 6 4
CLK32
HCLK
Figure 3. Timing Relationship with RESET_IN
MC9328MX21 Technical Data, Rev. 3.1 18 Freescale Semiconductor
Specifications
Table 12. Reset Module Timing Parameters
Ref No. 1 2 3 4 5 6 1.8V 0.10V Parameter Min Width of input POWER_ON_RESET Width of internal POWER_ON_RESET (CLK32 at 32 kHz) 7k to 32k-cycle stretcher for SDRAM reset 14k to 32k-cycle stretcher for internal system reset HRESERT and output reset at pin RESET_OUT Width of external hard-reset RESET_IN 4k to 32k-cycle qualifier 800 300 7 14 4 4 Max - 300 7 14 - 4 Min 800 300 7 14 4 4 Max - 300 7 14 - 4 ms ms Cycles of CLK32 Cycles of CLK32 Cycles of CLK32 Cycles of CLK32 3.0V 0.30V Unit
3.7
External DMA Request and Grant
The External DMA request is an active low signal to be used by devices external to i.MX21 processor to request the DMAC for data transfer. After assertion of External DMA request the DMA burst will start when the channel on which the External request is the source (as per the RSSR settings) becomes the current highest priority channel. The external device using the External DMA request should keep its request asserted until it is serviced by the DMAC. One External DMA request will initiate one DMA burst. The output External Grant signal from the DMAC is an active-low signal.When the following conditions are true, the External DMA Grant signal is asserted with the initiation of the DMA burst.
* * * The DMA channel for which the DMA burst is ongoing has request source as external DMA Request (as per source select register setting). REN and CEN bit of this channel are set. External DMA Request is asserted.
After the grant is asserted, the External DMA request will not be sampled until completion of the DMA burst. As the external request is synchronized, the request synchronization will not be done during this period. The priority of the external request becomes low for the next consecutive burst, if another DMA request signal is asserted. Worst case--that is, the smallest burst (1 byte read/write) timing diagrams are shown in Figure 4 and Figure 5. Minimum and maximum timings for the External request and External grant signals are present in Table 13. Figure 4 shows the minimum time for which the External Grant signal remains asserted when an External DMA request is de-asserted immediately after sensing grant signal active.
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 19
Specifications
Ext_DMAReq
Ext_DMAGrant tmin_assert
Figure 4. Assertion of DMA External Grant Signal
Figure 5 shows the safe maximum time for which External DMA request can be kept asserted, after sensing grant signal active such that a new burst is not initiated.
Ext_DMAReq Ext_DMAGrant tmax_req_assert Data read from External device Data written to External device
tmax_read tmax_write
NOTE: Assuming in worst case the data is read/written from/to External device as per the above waveform.
Figure 5. Safe Maximum Timings for External Request De-Assertion Table 13. DMA External Request and Grant Timing Parameters
3.0 V Parameter Description WCS tmin_assert Minimum assertion time of External Grant signal 8 hclk + 8.6 9 hclk - 20.66 8 hclk - 6.21 3 hclk - 15.87 BCS 8 hclk + 2.74 9 hclk - 6.7 8 hclk - 0.77 3 hclk - 8.83 WCS 8 hclk + 7.17 9 hclk - 17.96 8 hclk - 5.84 3 hclk - 15.9 BCS 8 hclk + 3.25 9 hclk - 8.16 8 hclk - 0.66 3 hclk - 9.12 ns ns ns ns 1.8 V Unit
tmax_req_assert Maximum External request assertion time after assertion of Grant signal tmax_read tmax_write Maximum External request assertion time after first read completion Maximum External request assertion time after completion of first write
3.8
3.8.1
3.8.1.1
BMI Interface Timing Diagram
Connecting BMI to ATI MMD Devices
ATI MMD Devices Drive the BMI_CLK/CS
In this mode MMD_MODE_SEL bit is set and MMD_CLKOUT bit is cleared. BMI_WRITE and BMI_CLK/CS are input signals to BMI driving by ATI MMD chip set. Output signal BMI_READ_REQ can be used as interrupt signal to inform MMD that data is ready in BMI TxFIFO for read access. MMD
MC9328MX21 Technical Data, Rev. 3.1 20 Freescale Semiconductor
Specifications
can write data to BMI RxFIFO anytime as CPU or DMA can move data out from RxFIFO much faster than the BMI interface. Overflow interrupt is generated if RxFIFO overflow is detected. Once this happens, the new coming data is ignored. 3.8.1.1.1 MMD Read BMI Timing
Figure 6 shows the MMD read BMI timing when the MMD drives clock. On each rising edge of BMI_CLK/CS BMI checks the BMI_WRITE logic level to determine if the current cycle is a read cycle. It puts data into the data bus and enables the data out on the rising edge of BMI_CLK/ CS if BMI_WRITE is logic high. The BMI_READ_REQ is negated one hclk cycle after the BMI_CLK/ CS rising edge of last data read. The MMD cannot issues read command when BMI_READ_REQ is low (no data in TxFIFO).
1T BMI_CLK/CS
BMI_READ_REQ Tds BMI_D[15:0] TxD1
Tdh
Trh
TxD2
Last TxD
BMI_WRITE Ts
Figure 6. MMD (ATI) Drives Clock, MMD Read BMI Timing (MMD_MODE_SEL=1, MASTER_MODE_SEL=0,MMD_CLKOUT=0) Table 14. MMD Read BMI Timing Table when MMD Drives Clock
Item Clock period write setup time read_req hold time transfer data setup time transfer data hold time Symbol 1T Ts Trh Tds Tdh Minimum 33.3 11 6 6 6 Typical - - - - Maximum - - 24 14 14 Unit ns ns ns ns ns
Note: All the timings assume that the hclk is running at 133 MHz. Note: The MIN period of the 1T is assumed that MMD latch data at falling edge. Note: If the MMD latch data at next rising edge, the ideally max clock can be as much as double, but because the BMI data pads are slow pads and it max frequency can only up to 18MHz, the max clock frequency can only up to 36 MHz.
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 21
Specifications
3.8.1.1.2
MMD Write BMI Timing
Figure 7 shows the MMD write BMI timing when MMD drives clock. On each falling edge of BMI_CLK/ CS BMI checks the BMI_WRITE logic level to determine if the current cycle is a write cycle. If the BMI_ WRITE is logic low, it latches data into the RxFIFO on each falling edge of BMI_CLK/CS signal.
BMI_CLK/CS
BMI_READ_REQ
Can be asserted any time
Can be asserted any time
BMI_D[15:0]
RxD1 Tds
RxD2
Last RxD
BMI_WRITE Ts Th
Figure 7. MMD (ATI) Drives Clock, MMD Write BMI Timing (MMD_MODE_SEL=1, MASTER_MODE_SEL=0, MMD_CLKOUT=0) Table 15. MMD Write BMI Timing
Item write setup time write hold time receive data setup time Symbol Ts Th Tds Minimum 11 0 5 Typical - - - Maximum - - - Unit ns ns ns
Note: All timings assume that the hclk is running at 133 MHz. Note: At this mode, the maximum frequency of the BMI_CLK/CS can be up to 36 MHz (doubles as maximum data pad speed).
3.8.1.2
BMI Drives the BMI_CLK/CS
In this mode MMD_MODE_SEL and MMD_CLKOUT are both set. The software must know which mode it is now (READ or WRITE). When the BMI_WRITE is high, BMI drives BMI_CLK/CS out if the TxFIFO is not emptied. When BMI_WRITE is low, user can write a 1 to READ bit of control register1 to issue a write cycle (MMD write BMI).
3.8.1.3
MMD Read BMI Timing
Figure 13 shows the MMD read BMI timing when BMI drives the BMI_CLK/CS. When the BMI_WRITE is high, the BMI drives BMI_CLK/CS out if data is written to TxFIFO (BMI_READ_REQ become high), BMI puts data into data bus and enable data out on the rising edge of BMI_CLK/CS. The MMD devices can latch the data on each falling edge of BMI_CLK/CS. It is recommended that the MMD do not change the BMI_WRITE signal from high to low when the BMI_READ_REQ is asserted. If user writes data to the TxFIFO when the BMI_WRITE is low, the BMI will drive BMI_CLK/CS out once the BMI_WRITE is changed from low to high.
MC9328MX21 Technical Data, Rev. 3.1 22 Freescale Semiconductor
Specifications
1T BMI_CLK/CS BMI_READ_REQ Tds BMI_D[15:0] TxD1 TxD2 Last TxD Trh
Tdh
BMI_WRITE DMA or CPU write data to TxFIFO
Figure 8. BMI Drives Clock, MMD Read BMI Timing (MASTER_MODE_SEL=0, MMD_MODE_SEL=1, MMD_CLKOUT=1) Table 16. MMD Read BMI Timing Table when BMI Drives Clock
Item Transfer data setup time Transfer data hold time Read_req hold time Symbol Tds Tdh Trh Minimum 2 2 2 Typical - - - Maximum 8 8 18 Unit ns ns ns
Note: In this mode, the max frequency of the BMI_CLK/CS can be up to 36MHz (double as max data pad speed). Note: The BMI_CLK/CS can only be divided by 2,4,8,16 from HCLK.
3.8.1.4
MMD Write BMI Timing
Figure 9 shows the MMD write BMI timing when BMI drives BMI_CLK/CS. When the BMI_WRITE signal is asserted, the BMI can write a 1 to READ bit of control register to issue a WRITE cycle. This bit is cleared automatically when the WRITE operation is completed. In a WRITE burst the MMD will write COUNT+1 data to the BMI. The user can issue another WRITE operation if the MMD still has data to write after the first operation completed. The BMI can latch the data either at falling edge or the next rising edge of the BMI_CLK/CS according to the DATA_LATCH bit. When the DATA_LATCH bit is set, the BMI latch data at the next rising edge and latch the last data using the internal clock. BMI_WRITE signal can not be negated when the WRITE operation is proceeding.
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 23
Specifications
Total has COUNT+1 clocks in one burst
BMI_CLK/CS
BMI_READ_REQ
Can be asserted any time
Can be asserted any time
BMI_D[15:0]
RxD1 Tds1
RxD2 Tds2
Last RxD
BMI_WRITE A 1 is written to READ bit of control register
Figure 9. BMI Drives Clock, MMD Write BMI Timing (MASTER_MODE_SEL=0, MMD_MODE_SEL=1, MMD_CLKOUT=1) Table 17. MMD Write BMI Timing Table when BMI Drives Clock
Item Receive data setup time1 Receive data setup time2 Symbol Tds1 Tds2 Minimum 14 14 Typical - - Maximum - - Unit ns ns
Note: The BMI_CLK/CS can only be up to 30MHz if BMI latch data at the falling edge and can be up to 36MHz (double as max data pad speed) if BMI latch data at the next rising edge. Note: Tds1 is the receive data setup time when BMI latch data at the falling edge. Note: Tds2 is the receive data setup time when BMI latch data at the next rising edge.
3.8.2
Connecting BMI to External Bus Master Devices
In this mode both MASTER_SEL bit and MMD_MODE_SEL bit are cleared and the MMD_CLKOUT bit is no useful. BMI_WRITE and BMI_CLK/CS are input signals driving by the external bus master. The Output signal BMI_READ_REQ can be used as an interrupt signal to inform external bus master that data is ready in the BMI TxFIFO for a read access. The external bus master can write data to the BMI RxFIFO anytime since the CPU or DMA can move data out from RxFIFO much faster than the BMI interface. An overflow interrupt is generated if RxFIFO overflow is detected. Once this happens, the new coming data is ignored. Each falling edge of BMI_CLK/CS will determine if the current cycle is read or write cycle. It drives data and enables data out if BMI_WRITE is logic high. The D_EN signal remains active only while BMI_CLK/ CS is logic low and BMI_WRITE is logic high. Each rising edge of BMI_CLK/CS will determine if data should be latched to RxFIFO from the data bus.
MC9328MX21 Technical Data, Rev. 3.1 24 Freescale Semiconductor
Specifications
BMI_CLK/CS
BMI_READ_REQ BMI_D[15:0] Ts BMI_WRITE
Ttds
Ttdh
Trdh
Trh
TxD
Ts
RxD
Last TxD
Th Read BMI Write BMI Read BMI
Figure 10. Memory Interface Slave Mode, External Bus Master Read/Write to BMI Timing (MMD_MODE_SEL=0, MASTER_MODE_SEL=0) Table 18. External Bus Master Read/Write to BMI Timing Table
Item Write setup time Write hold time Receive data hold time Transfer data setup time Transfer data hold time Read_req hold time Symbol Ts Th Trdh Ttds Ttdh Trh Minimum 11 0 3 6 6 6 Typical - - - - - - Maximum - - - 14 14 24 Unit ns ns ns ns ns ns
Note: All the timings are assumed that the hclk is running at 133 MHz.
3.8.3
Connecting BMI to External Bus Slave Devices
In this mode the BMI_WRITE, BMI_READ and BMI_CLK/CS are output signals driving by the BMI module. The output signal BMI_READ_REQ is still driving active-in on a write cycle, but it can be ignored in this case. Instead, it is used to trigger internal logic to generate the read or write signals. Data write cycles are continuously generated when TxFIFO is not emptied. To issue a read cycle, the user can write a value of 1 to the READ bit of control register. This bit is cleared automatically when the read operation is completed. A read cycle reads COUNT+1 data from the external bus slave. The user can write a 1 to the READ bit while there is still data in the TxFIFO, but the read cycle will not start until all data in the TxFIFO is emptied. If the read cycle begins, the write operation also cannot begin until this read cycle complete. In this master mode operation, Int_Clk is derived from HCLK through an integer divider DIV of BMI control register and it is used to control the read/write cycle timing by generate WRITE and CLK/CS signals.
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 25
Specifications
3.8.3.1
Memory Interface Master Mode Without WAIT Signal
The WAIT control bit (BMICTLR1[29]) is used in this mode. When this bit is cleared (default), the BMI_WAIT signal is ignored and the CS cycle is terminated by Wait State (WS) control bits. Figure 11 shows the BMI timing when the WAIT bit is cleared.
1+ws 1+ws 1+ws 1+ws
Int_Clk (reference only) Int_write (reference only) BMI_CLK/CS BMI_READ_REQ
BMI_D[15:0]
TxD1
TxD2
Last TxD
RxD1
Tdh
RxD2
BMI_WRITE BMI_READ BMI write BMI write BMI write
A 1 is written to READ bit of control reg1 DMA or CPU write data to TxFIFO On the next Int_Clk BMI issues a write cycle BMI_READ_REQ is still logic high, BMI issues next write cycle
Figure 11. Memory Interface Master Mode, BMI Read/Write to External Slave Device Timing without Wait Signal (MMD_MODE_SEL=0, MASTER_MODE_SEL=1)
3.8.3.2
Memory Interface Master Mode with WAIT Signal
When the WAIT control bit is set, the BMI_WAIT signal is used and the CS cycle is terminated upon sampling a logic high BMI_WAIT signal. Figure 12 shows the BMI write timing when the WAIT bit is set. When the BMI_WRITE is asserted, the BMI will detect the BMI_WAIT signal on every falling edge of the Int_Clk. When it detected the high level of the BMI_WAIT, the BMI_WRITE will be negated after 1+WS Int_Clk period. If the BMI_WAIT is always high or already high before BMI_WRITE is asserted, this timing will same as without WAIT signal. So the BMI_WRITE will be asserted at least for 1+WS Int_Clk period.
MC9328MX21 Technical Data, Rev. 3.1 26 Freescale Semiconductor
Specifications
1+ws Int_Clk (reference only) BMI_CLK/CS BMI_D[15:0] TXD_a BMI_READ BMI_WRITE TXD_b 1+ws
BMI_WAIT
Figure 12. Memory Interface Master Mode, BMI Write to External Slave Device Timing with Wait Signal (MMD_MODE_SEL=0, MASTER_MODE_SEL=1,WAIT=1)
Figure 13 shows the BMI read timing when the WAIT bit is set. As write timing, when the BMI_READ is asserted, the BMI will detect the BMI_WAIT signal on every falling edge of the Int_Clk. When it detected the high level of the BMI_WAIT, the BMI_READ will be negated after 1+WS Int_Clk period. If the BMI_WAIT is always high or already high before BMI_READ is asserted, this timing will same as without WAIT signal. So the BMI_READ will be asserted at least for 1+WS Int_Clk period.
1+ws Int_Clk (reference only) BMI_CLK/CS BMI_D[15:0] RXD_a BMI_WRITE BMI_READ RXD_b 1+ws
BMI_WAIT
Figure 13. Memory Interface Master Mode, BMI Read to External Slave Device Timing with Wait Signal (MMD_MODE_SEL=0, MASTER_MODE_SEL=1,WAIT=1)
3.9
CSPI Timing Diagrams
To use the internal transmit (TX) and receive (RX) data FIFOs when the CSPI1 module is configured as a master, two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY signal (input). The SPI 1 Sample Period Control Register (PERIODREG1) and the SPI 2 Sample Period Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for either CSPI1 or CSPI2. When the CSPI1 module is configured as a slave, the user can configure the SPI 1 Control Register (CONTROLREG1) to match the external CSPI master's timing. In this configuration, SS
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 27
Specifications
becomes an input signal, and is used to latch data into or load data out to the internal data shift registers, as well as to increment the data FIFO.
2 SS 1 SPIRDY 4 3 5
SCLK, MOSI, MISO
Figure 14. Master CSPI Timing Diagram Using SPI_RDY Edge Trigger
SS
SPIRDY
SCLK, MOSI, MISO
Figure 15. Master CSPI Timing Diagram Using SPI_RDY Level Trigger
SS (output)
SCLK, MOSI, MISO
Figure 16. Master CSPI Timing Diagram Ignore SPI_RDY Level Trigger
SS (input)
SCLK, MOSI, MISO
Figure 17. Slave CSPI Timing Diagram FIFO Advanced by BIT COUNT
SS (input) 6 SCLK, MOSI, MISO 7
Figure 18. Slave CSPI Timing Diagram FIFO Advanced by SS Rising Edge
MC9328MX21 Technical Data, Rev. 3.1 28 Freescale Semiconductor
Specifications
Table 19. Timing Parameters for Figure 14 through Figure 18
Ref No. 1 2 3 4 5 6 7 Parameter SPI_RDY to SS output low SS output low to first SCLK edge Last SCLK edge to SS output high SS output high to SPI_RDY low SS output pulse width SS input low to first SCLK edge SS input pulse width Minimum 2T 1 3*Tsclk 2 2*Tsclk 0 Tsclk + WAIT 3 T T Maximum - - - - - - - Unit ns ns ns ns ns ns ns
1. T = CSPI system clock period (PERCLK2). 2. Tsclk = Period of SCLK. 3. WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control Register.
3.10
LCD Controller
This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD controller with various display configurations, refer to the LCD controller chapter of the i.MX21 Reference Manual.
T1 LSCLK
LD[17:0] T2 T3
Figure 19. SCLK to LD Timing Diagram Table 20. LCDC SCLK Timing Parameters
3.0 0.3V Symbol Parameter Minimum T1 T2 T3 SCLK period Pixel data setup time Pixel data up time 23 11 11 Maximum 2000 - - ns ns ns Unit
The pixel clock is equal to LCDC_CLK / (PCD + 1). When it is in CSTN, TFT or monochrome mode with bus width = 1, SCLK is equal to the pixel clock. When it is in monochrome with other bus width settings, SCLK is equal to the pixel clock divided by bus width. The polarity of SCLK and LD can also be programmed. Maximum frequency of SCLK is HCLK / 3 for TFT and CSTN, otherwise LD output will be incorrect.
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 29
Specifications
Non-display region
T1 T3
Display region T4
VSYN HSYN OE LD[17:0]
T2
Line Y
Line 1
Line Y
T5 HSYN SCLK OE LD[15:0]
T6
XMAX
T7
(0,1)
(0,2)
(0,X-1)
Figure 20. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing Table 21. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing
Symbol T1 T2 T3 T4 T5 T6 T7 Description End of OE to beginning of VSYN HSYN period VSYN pulse width End of VSYN to beginning of OE HSYN pulse width End of HSYN to beginning to OE End of OE to beginning of HSYN Minimum T5+T6+T7-1 - T2 1 1 3 1 Value (VWAIT1*T2)+T5+T6+T7-1 XMAX+T5+T6+T7 VWIDTH*T2 (VWAIT2*T2)+1 HWIDTH+1 HWAIT2+3 HWAIT1+1 Unit Ts Ts Ts Ts Ts Ts Ts
Note: * Ts is the SCLK period. * VSYN, HSYN and OE can be programmed as active high or active low. In Figure 20, all 3 signals are active low. * SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 20, SCLK is always active. * XMAX is defined in number of pixels in one line.
MC9328MX21 Technical Data, Rev. 3.1 30 Freescale Semiconductor
Specifications
XMAX SCLK
LD
D320
D1
D2
D320
SPL_SPR
T1
HSYN
T2
T3
T2
CLS PS
T4 T5 T6 T7
T4
T7
REV
Figure 21. Sharp TFT Panel Timing Table 22. Sharp TFT Panel Timing
Symbol T1 T2 T3 T4 T5 T6 T7 Note: * * * Description SPL/SPR pulse width End of LD of line to beginning of HSYN End of HSYN to beginning of LD of line CLS rise delay from end of LD of line CLS pulse width PS rise delay from CLS negation REV toggle delay from last LD of line Minimum - 1 4 3 1 0 1 Value 1 HWAIT1+1 HWAIT2 + 4 CLS_RISE_DELAY+1 CLS_HI_WIDTH+1 PS_RISE_DELAY REV_TOGGLE_DELAY+1 Unit Ts Ts Ts Ts Ts Ts Ts
Falling of SPL/SPR aligns with first LD of line. Falling of PS aligns with rising edge of CLS. REV toggles in every HSYN period.
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 31
Specifications T1
VSYN
T1
T2
HSYN SCLK
T3
XMAX
T4
T2
Ts
LD[15:0]
Figure 22. Non-TFT Mode Panel Timing Table 23. Non-TFT Mode Panel Timing
Symbol T1 T2 T3 T4 Description HSYN to VSYN delay HSYN pulse width VSYN to SCLK SCLK to HSYN Minimum 2 1 - 1 Value HWAIT2+2 HWIDTH+1 0 Unit Tpix Tpix - Tpix
T3 Ts
HWAIT1+1
Note: * Ts is the SCLK period while Tpix is the pixel clock period. * VSYN, HSYN and SCLK can be programmed as active high or active low. In Figure 67, all these 3 signals are active high. * When it is in CSTN mode or monochrome mode with bus width = 1, T3 = Tpix = Ts. * When it is in monochrome mode with bus width = 2, 4, and 8, T3 = 1, 2 and 4 Tpix respectively.
MC9328MX21 Technical Data, Rev. 3.1 32 Freescale Semiconductor
Specifications
3.11
Smart LCD Controller
T2 LCD_CS LCD_CLK (LCD_DATA[6]) T4 SDATA (LCD_DATA[7]) MSB T6 RS RS=0 command data, RS=1 display data SCKPOL = 1, CSPOL = 0 T2 LCD_CS LCD_CLK (LCD_DATA[6]) T4 SDATA (LCD_DATA[7]) MSB T6 RS=0 command data, RS=1 display data SCKPOL = 0, CSPOL = 0 T2 LCD_CS LCD_CLK (LCD_DATA[6]) T4 SDATA (LCD_DATA[7]) MSB T6 RS RS=0 command data, RS=1 display data SCKPOL = 1, CSPOL = 1 T5 T7 LSB T1 T3 T5 T7 LSB T1 T3 T5 T7 LSB T1 T3
RS
T2 LCD_CS LCD_CLK (LCD_DATA[6]) T4 SDATA (LCD_DATA[7]) MSB T6 RS RS=0 command data, RS=1 display data SCKPOL = 0, CSPOL = 1 T5 T1
T3
T7 LSB
Figure 23. SLCDC Serial Transfer Timing
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 33
Specifications
Table 24. SLCDC Serial Transfer Timing
Symbol T1 T2 T3 T4 T4 T6 T7 Description Pixel clock period Chip select setup time Chip select hold time Data setup time Data hold time Register select setup time Register select hold time Minimum 42 5 5 5 5 5 5 Maximum 962 - - - - - - Unit ns ns ns ns ns ns ns
LCD_CLK T4 LCD_RS T1 LCD_CS T2 LCD_DATA[15:0] T3 display data T5
command data
CSPOL = 0
LCD_CLK T4 LCD_RS T1 LCD_CS T2 LCD_DATA[15:0] T3 display data T5
command data
CSPOL = 1
Figure 24. SLCDC Parallel Transfers Timing Table 25. SLCDC Parallel Transfers Timing
Symbol T1 T2 T3 T4 T5 Description Pixel clock period Data setup time Data hold time Register select setup time Register select hold time Minimum 23 5 5 5 5 Maximum 962 - - - - Unit ns ns ns ns ns
MC9328MX21 Technical Data, Rev. 3.1 34 Freescale Semiconductor
Specifications
3.12
Multimedia Card/Secure Digital Host Controller
The DMA interface block controls all data routing between the external data bus (DMA access), internal MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the MMC/ SD module (inner system) and the application (user programming).
3a 3b
Bus Clock
1
2 4b
4a 5a
CMD_DAT Input
Valid Data
5b
Valid Data
7
CMD_DAT Output
Valid Data Valid Data
6a
6b
Figure 25. Chip-Select Read Cycle Timing Diagram Table 26. SDHC Bus Timing Parameters
Ref No. 1 2 3a 3b 4a 4b 5a 5b 6a 6b 7 1.8 V 0.1 V Parameter Min CLK frequency at Data transfer Mode (PP)1--10/30 cards CLK frequency at Identification Mode Clock high time1--10/30 cards Clock low time1--10/30 cards
2
3.0 V 0.3 V Unit Min 0 0 10/50 10/50 - - 5/5 5/5 5/5 5/5 0 Max 25/5 400 - - 10/50 10/50 - - - - 14 MHz kHz ns ns ns ns ns ns ns ns ns
Max 25/5 400 - - 10/50 (5.00)3 14/67 (6.67)3 - - - - 16
0 0 6/33 15/75 - - 5.7/5.7 5.7/5.7 5.7/5.7 5.7/5.7 0
Clock fall time1--10/30 cards Clock rise time1--10/30 cards
Input hold time3--10/30 cards Input setup time3--10/30 cards
Output hold time3--10/30 cards Output setup time --10/30 cards Output delay time3
3
1. CL 100 pF / 250 pF (10/30 cards) 2. CL 250 pF (21 cards) 3. CL 25 pF (1 card)
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 35
Specifications
3.12.1
Command Response Timing on MMC/SD Bus
The card identification and card operation conditions timing are processed in open-drain mode. The card response to the host command starts after exactly NID clock cycles. For the card address assignment, SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and card response is NCR clock cycles as illustrated in Figure 26. The symbols for Figure 26 through Figure 30 are defined in Table 27.
Table 27. State Signal Parameters for Figure 26 through Figure 30
Card Active Symbol Z D * CRC Definition High impedance state Data bits Repetition Cyclic redundancy check bits (7 bits) Symbol S T P E Host Active Definition Start bit (0) Transmitter bit (Host = 1, Card = 0) One-cycle pull-up (1) End bit (1)
NID cycles Host Command CMD S T Content CRC E Z ****** Z ST CID/OCR Content ZZZ
Identification Timing NCR cycles Host Command CMD S T Content CRC E Z ****** Z ST CID/OCR Content ZZZ
SET_RCA Timing
Figure 26. Timing Diagrams at Identification Mode
After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in Figure 27, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the responding card. The other two diagrams show the separating periods NRC and NCC.
MC9328MX21 Technical Data, Rev. 3.1 36 Freescale Semiconductor
Specifications
NCR cycles Host Command CMD S T Content CRC E Z Z P ****** PST Response Content CRC E Z Z Z
Command response timing (data transfer mode)
NRC cycles Response CMD S T Content CRC E Z ****** Z ST Host Command Content CRC E Z Z Z
Timing response end to next CMD start (data transfer mode)
NCC cycles Host Command CMD S T Content CRC E Z ****** Z ST Host Command Content CRC E Z Z Z
Timing of command sequences (all modes)
Figure 27. Timing Diagrams at Data Transfer Mode
Figure 28 shows basic read operation timing. In a read operation, the sequence starts with a single block read command (which specifies the start address in the argument field). The response is sent on the SD_CMD lines as usual. Data transmission from the card starts after the access time delay NAC , beginning from the last bit of the read command. If the system is in multiple block read mode, the card sends a continuous flow of data blocks with distance NAC until the card sees a stop transmission command. The data stops two clock cycles after the end bit of the stop command.
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 37
Specifications
NCR cycles Host Command CMD S T Content CRC E Z Z P ****** P S T Response Content CRC E Z
DAT
Z****Z
Z Z P ****** P S D D D D
*****
NAC cycles
Read Data Timing of single block read
NCR cycles Host Command CMD S T Content CRC E Z Z P ****** P S T Response Content CRC E Z
DAT
Z****Z
ZZP
******
P S DDDD
*****
P
*****
P S DDDD
*****
Read Data NAC cycles NAC cycles
Read Data
Timing of multiple block read
NCR cycles Host Command CMD S T Content CRC E Z Z P ****** P S T NST DAT D D D D ***** DDDDE Z Z Z ***** Timing of stop command (CMD12, data transfer mode) Response Content CRC E Z
Valid Read Data
Figure 28. Timing Diagrams at Data Read
Figure 29 shows the basic write operation timing. As with the read operation, after the card response, the data transfer starts after NWR cycles. The data is suffixed with CRC check bits to allow the card to check for transmission errors. The card sends back the CRC check result as a CC status token on the data line. If there was a transmission error, the card sends a negative CRC status (101); otherwise, a positive CRC status (010) is returned. The card expects a continuous flow of data blocks if it is configured to multiple block mode, with the flow terminated by a stop transmission command.
MC9328MX21 Technical Data, Rev. 3.1 38 Freescale Semiconductor
NCR cycles Host Command Response ****** Content ****** PST CRC E Z Z P PP P CMD S T Content CRC E Z Z P
Freescale Semiconductor
DAT Z****Z Content Content Write Data Timing of the block write command NWR cycles CRC status Z****Z Z ZZPPS DAT Z ZZPPS CRC E Z Z S Status ES L*L EZ CRC E Z Z X X X X X X X X X X X X X X X X Z Busy CMD E Z Z P ****** Content CRC E Z Z S Status EZPPS Content CRC E Z Z S Status ES L*L DAT Z Z P P S PPP EZ DAT Z Z P P S Content Write Data CRC status CRC E Z Z X X X X X X X X Z P P S Content Write Data CRC status NWR cycles CRC E Z Z X X X X X X X X X X X X X X X X Z Busy NWR cycles Timing of the multiple block write command
Figure 29. Timing Diagrams at Data Write
The stop transmission command may occur when the card is in different states. Figure 30 shows the different scenarios on the bus.
MC9328MX21 Technical Data, Rev. 3.1
Specifications
39
40
NCR cycles Host Command Card Response ****** PST Content CRC E Z Z Z ST CMD S T Content CRC E Z Z P Host Command Content CRC E DAT D D D D D D D D D D D D D E Z Z S L ****** Write Data Busy (Card is programming) DAT D D D D D D D Z Z S CRC E Z Z S L ****** EZZ Z Z Z ZZ ZZ ZZ ZZ ZZ Z Z ZZ Z ZZ ZZ ZZ Stop transmission during data transfer from the host. EZZ Z Z Z ZZ ZZ ZZ ZZ ZZ Z Z ZZ Z ZZ ZZ ZZ Stop transmission during CRC status transfer from the card. DAT S L ****** EZZ Z Z Z ZZ ZZ ZZ ZZ ZZ Z Z ZZ Z ZZ ZZ ZZ Stop transmission received after last data block. Card becomes busy programming. DAT Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z S L ****** EZZ Z Z Z ZZ ZZ ZZ ZZ ZZ Z Z ZZ Z ZZ ZZ ZZ Stop transmission received after last data block. Card becomes busy programming.
Specifications
Access time delay cycle
Command response cycle
Parameter
Identification response cycle
NID
Symbol
NCR
NAC
2
Minimum
2
5
MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL)
Figure 30. Stop Transmission During Different Scenarios
Table 28. Timing Values for Figure 26 through Figure 30
MC9328MX21 Technical Data, Rev. 3.1
Maximum
64
5
TAAC + NSAC
Unit
Clock cycles
Clock cycles
Clock cycles
Freescale Semiconductor
Specifications
Table 28. Timing Values for Figure 26 through Figure 30 (Continued)
Parameter Command read cycle Command-command cycle Command write cycle Stop transmission cycle Symbol NRC NCC NWR NST Minimum 8 8 2 2 Maximum - - - 2 Unit Clock cycles Clock cycles Clock cycles Clock cycles
TAAC: Data read access time -1 defined in CSD register bit[119:112] NSAC: Data read access time -2 in CLK cycles (NSAC*100) defined in CSD register bit[111:104]
3.12.2
SDIO-IRQ and ReadWait Service Handling
In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the interrupt response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data in this mode. The memory controller generates an interrupt according to this low and the system interrupt continues until the source is removed (SD_DAT[1] returns to its high level). In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the Interrupt Period during the data access, and the controller must sample SD_DAT[1] during this short period to determine the IRQ status of the attached card. The interrupt period only happens at the boundary of each block (512 bytes).
CMD
ST
Content
CRC E Z Z P S
Response
EZZZ
******
ZZZ
DAT[1] For 4-bit
Interrupt Period
S
Block Data
E
IRQ
S
Block Data
E
IRQ
LH DAT[1] For 1-bit Interrupt Period
Figure 31. SDIO IRQ Timing Diagram
ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In this mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps the clock running, and allows the user to submit commands as normal. After all commands are submitted, the user can switch back to the data transfer operation and all counter and status values are resumed as access continues.
CMD
******
P S T CMD52
CRC E Z Z Z
******
DAT[1] S For 4-bit DAT[2] S For 4-bit
Block Data
EZ Z L H
S
Block Data
E
Block Data
E Z Z L L L L L L L L L L L L L L L L L L L L L HZ S
Block Data
E
Figure 32. SDIO ReadWait Timing Diagram
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 41
Specifications
3.13
3.13.1
External Memory Interface (EMI) Electricals
NAND-Flash Controller (NFC) Interface
Figure 33, Figure 34, Figure 35, and Figure 36 depict the relative timing requirements among different signals of the NFC at module level, and Table 29 lists the timing parameters. The NAND Flash Controller (NFC) timing parameters are based on the internal NFC clock generated by the Clock Controller module, where time T is the period of the NFC clock in ns. Per the i.MX21 Reference Manual, specifically the Phase-Locked (PLL), Clock, and Reset Controller chapter, the NFC clock is derived from the same clock which drives the CPU clock (FCLK) that is fed through the NFCDIV block to generate the NFC clock. The relationship between the NFC clock and the external timing parameters of the NFC is provided in Table 29. Table 29 also provides two examples of external timing parameters with NFC clock frequencies of 22.17 MHz and 33.25 MHz. For example, assuming a 266 MHz FCLK (CPU clock), NFCDIV should be set to divide-by-12 to generate a 22.17 MHz NFC clock and divide-by-8 to generate a 33.25 MHz NFC clock. The user should compare the parameters of the selected NAND Flash memory with the NFC external timing parameters to determine the proper NFC clock. The maximum NFC clock allowed is 66 MHz. It should also be noted that the default NFC clock on power up is 16.63 MHz.
NFCLE NF1 NF3 NFCE NF5 NF2 NF4
NFWE NF6 NFALE
NF7
NF8 NFIO[7:0] command
NF9
Figure 33. Command Latch Cycle Timing DIagram
MC9328MX21 Technical Data, Rev. 3.1 42 Freescale Semiconductor
Specifications
NFCLE NF1 NFCE NF4 NF3 NF5 NFWE NF6 NF7 NFALE NF8 NFIO[7:0] Address
Time it takes for SW to issue the next address command
NF9 Address
Figure 34. Address Latch Cycle Timing DIagram
NFCLE NF1 NF3 NFCE
NF10 NF5 NFWE NF6 NFALE NF8 NFIO[15:0] NF9 NF11
NF4
Data to Flash
Figure 35. Write Data Latch Timing DIagram
NFCLE NFCE NF3 NF13 NFRE NF16 NFRB NF14 NF15
NF17
NFIO[15:0] NF12
Data from Flash
Figure 36. Read Data Latch Timing Diagram
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 43
Specifications
Table 29. NFC Target Timing Parameters1,2
Relationship to NFC Clock Period (T) Min NF1 NF2 NF3 NF4 NF5 NF6 NF7 NF8 NF9 NFCLE Setup Time NFCLE Hold Time NFCE Setup Time NFCE Hold Time NF_WP Pulse Width NFALE Setup Time NFALE Hold Time Data Setup Time Data Hold Time tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH tRR tRP tRC tREH tDSR tDHR T T T T T T T T T 2T T 4T 1.5T 2T 0.5T 15 0 Max - - - - - - - - - - - - - - - - - NFC Clock 22.17 MHz T = 45 ns Min 45 45 45 45 45 45 45 45 45 90 45 180 67.5 90 22.5 15 0 Max - - - - - - - - - - - - - - - - - NFC Clock 33.25 MHz T = 30 ns Min 30 30 30 30 30 30 30 30 30 60 30 120 45 60 15 15 0 Max - - - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ID
Parameter
Symbol
Unit
NF10 Write Cycle Time NF11 NFWE Hold Time NF12 Ready to NFRE Low NF13 NFRE Pulse Width NF14 READ Cycle Time NF15 NFRE High Hold Time NF16 Data Setup on READ NF17 Data Hold on READ
1. High is defined as 80% of signal value and low is defined as 20% of signal value. All timings are listed according to this NFC clock frequency (multiples of NFC clock period) except NF16, which is not NFC clock related. 2. The read data is generated by the NAND Flash device and sampled with the internal NFC clock.
MC9328MX21 Technical Data, Rev. 3.1 44 Freescale Semiconductor
Specifications
3.14
Pulse-Width Modulator
The PWM can be programmed to select one of two clock signals as its source frequency. The selected clock signal is passed through a divider and a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin.
2a
System Clock
1 3b
2b 3a 4a
PWM Output
4b
Figure 37. PWM Output Timing Diagram Table 30. PWM Output Timing Parameters
1.8 V 0.1 V Ref No. Parameter Minimum 1 2a 2b 3a 3b 4a 4b System CLK frequency1 Clock high time1 Clock low time1 Clock fall time1 Clock rise time1 Output delay time1 Output setup time1 0 12.29 9.91 - - 9.37 8.71 Maximum 45 - - 0.5 0.5 - - Minimum 0 12.29 9.91 - - 3.61 3.03 Maximum 45 - - 0.5 0.5 - - MHz ns ns ns ns ns ns 3.0 V 0.3 V Unit
1. CL of PWMO = TBD
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 45
Specifications
3.15
SDRAM Memory Controller
The following figures (Figure 38 through Figure 41) and their associated tables specify the timings related to the SDRAMC module in the i.MX21.
1 SDCLK 2 3S CS 3
3S RAS 3S 3H CAS 3S 3H WE
3H
3H
4S ADDR
4H COL/BA 8 5 6 Data 7 3S
ROW/BA
DQ
DQM 3H
Note: CKE is high during the read/write cycle.
Figure 38. SDRAM Read Cycle Timing Diagram Table 31. SDRAM Read Cycle Timing Parameter
Ref No. 1 2 3 3S 3H 1.8 V 0.1 V Parameter Minimum SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time CS, RAS, CAS, WE, DQM setup time CS, RAS, CAS, WE, DQM hold time 3.00 3.00 7.5 4.78 3.03 Maximum - - - - - Minimum 3 3 7.5 3 2 Maximum - - - - - ns ns ns ns ns 3.0 V 0.3 V Unit
MC9328MX21 Technical Data, Rev. 3.1 46 Freescale Semiconductor
Specifications
Table 31. SDRAM Read Cycle Timing Parameter (Continued)
Ref No. 4S 4H 5 5 5 6 7 7 7 8 Address setup time Address hold time SDRAM access time (CL = 3) SDRAM access time (CL = 2) SDRAM access time (CL = 1) Data out hold time Data out high-impedance time (CL = 3) Data out high-impedance time (CL = 2) Data out high-impedance time (CL = 1) Active to read/write command period (RC = 1) 1.8 V 0.1 V Parameter Minimum 3.67 2.95 - - -
2
3.0 V 0.3 V Unit Minimum 2 2 - - -
2
Maximum - -
5.4 6.0
Maximum - -
5.4 6.0
ns ns ns ns ns ns ns ns ns ns
- - tHZ1 tHZ1 - -
- - tHZ1 tHZ1 -
2
- - - tRCD2
- - - tRCD
-
1. tHZ = SDRAM data out high-impedance time, external SDRAM memory device dependent parameter. 2. tRCD = SDRAM clock cycle time. The tRCD setting can be found in the i.MX21 reference manual.
SDCLK 1 CS 3 2
RAS
6
CAS
WE 4 ADDR 5 7 COL/BA 8 DQ DATA 9
/ BA
ROW/BA
DQM
Figure 39. SDRAM Write Cycle Timing Diagram
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 47
Specifications
Table 32. SDRAM Write Cycle Timing Parameter
Ref No. 1 2 3 4 5 6 7 8 9 1.8 V 0.1 V Parameter Minimum SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time Address setup time Address hold time Precharge cycle period1 Active to read/write command delay Data setup time Data hold time 3.00 3.00 7.5 3.67 2.95 tRP2 tRCD2 3.41 2.45 Maximum - - - - - - - - - Minimum 3 3 7.5 2 2 tRP2 tRCD2 2 2 Maximum - - - - - - - - - ns ns ns ns ns ns ns ns ns 3.0 V 0.3 V Unit
1. Precharge cycle timing is included in the write timing diagram. 2. tRP and tRCD = SDRAM clock cycle time. These settings can be found in the i.MX21 reference manual.
SDCLK 1 CS 3 2
RAS
6
CAS 7 7
WE 4 ADDR BA 5 ROW/BA
DQ
DQM
Figure 40. SDRAM Refresh Timing Diagram
MC9328MX21 Technical Data, Rev. 3.1 48 Freescale Semiconductor
Specifications
Table 33. SDRAM Refresh Timing Parameters
Ref No. 1 2 3 4 5 6 7 1.8 V 0.1 V Parameter Minimum SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time Address setup time Address hold time Precharge cycle period Auto precharge command period 3.00 3.00 7.5 3.67 2.95 tRP1 tRC1 Maximum - - - - - - - Minimum 3 3 7.5 2 2 tRP1 tRC1 Maximum - - - - - - - ns ns ns ns ns ns ns 3.0 V 0.3 V Unit
1. tRP and tRC = SDRAM clock cycle time. These settings can be found in the i.MX21 reference manual.
SDCLK
CS
RAS
CAS
WE
ADDR
BA
DQ
DQM
CKE
Figure 41. SDRAM Self-Refresh Cycle Timing Diagram
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 49
Specifications
3.16
Synchronous Serial Interface
The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode, the transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous mode, the transmitter and receiver each have their own clock and frame synchronization signals. Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In gated clock mode, the clock functions only during transmission. The internal and external clock timing diagrams are shown in Figure 42 through Figure 45. Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is typically used in star or ring-time division multiplex networks with other processors or codecs, allowing interface to time division multiplexed networks without additional logic. Use of the gated clock is not allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to communicate with a wide variety of devices. The SSI can be connected to 4 set of ports, SAP, SSI1, SSI2 and SSI3.
1
CK Output
2
FS (bl) Output
4
6
FS (wl) Output
8 12
10
STXD Output
11
31
SRXD Input
32
Note: SRXD input in synchronous mode only.
Figure 42. SSI Transmitter Internal Clock Timing Diagram
MC9328MX21 Technical Data, Rev. 3.1 50 Freescale Semiconductor
Specifications 1
CK Output
3
FS (bl) Output
5
7
FS (wl) Output
9
13 14
SRXD Input
Figure 43. SSI Receiver Internal Clock Timing Diagram
15 16
CK Input
17
18
FS (bl) Input
20
22
FS (wl) Input
24
26
STXD Output
27
28
33
SRXD Input Note: SRXD Input in Synchronous mode only
34
Figure 44. SSI Transmitter External Clock Timing Diagram
15 16
CK Input
17
19
FS (bl) Input
21
23
FS (wl) Input
25
29
SRXD Input
30
Figure 45. SSI Receiver External Clock Timing Diagram
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 51
Specifications
Table 34. SSI to SAP Ports Timing Parameters
Ref No. 1.8 V 0.1 V Parameter Minimum Maximum Minimum Maximum Internal Clock Operation1 (SAP Ports) 1 2 3 4 5 6 7 8 9 10 11a 11b 12 13 14 (Tx/Rx) CK clock period1 (Tx) CK high to FS (bl) high (Rx) CK high to FS (bl) high (Tx) CK high to FS (bl) low (Rx) CK high to FS (bl) low (Tx) CK high to FS (wl) high (Rx) CK high to FS (wl) high (Tx) CK high to FS (wl) low (Rx) CK high to FS (wl) low (Tx) CK high to STXD valid from high impedance (Tx) CK high to STXD high (Tx) CK high to STXD low (Tx) CK high to STXD high impedance SRXD setup time before (Rx) CK low SRXD hold time after (Rx) CK low 90.91 -3.30 -3.93 -3.30 -3.93 -3.30 -3.93 -3.30 -3.93 -2.44 -2.44 -2.44 -2.67 23.68 0 - -1.16 -1.34 -1.16 -1.34 -1.16 -1.34 -1.16 -1.34 -0.60 -0.60 -0.60 -0.99 - - 90.91 -2.98 -4.18 -2.98 -4.18 -2.98 -4.18 -2.98 -4.18 -2.65 -2.65 -2.65 -2.65 22.09 0 - -1.10 -1.43 -1.10 -1.43 -1.10 -1.43 -1.10 -1.43 -0.98 -0.98 -0.98 -0.98 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3.0 V 0.3 V Unit
External Clock Operation (SAP Ports) 15 16 17 18 19 20 21 22 23 24 25 26 27a 27b 28 29 30 (Tx/Rx) CK clock period1 90.91 36.36 36.36 10.24 10.89 10.24 10.89 10.24 10.89 10.24 10.89 12.08 10.80 10.80 12.08 0.37 0 - - - 19.50 21.27 19.50 21.27 19.50 21.27 19.50 21.27 19.36 19.36 19.36 19.36 - - 90.91 36.36 36.36 7.16 7.63 7.16 7.63 7.16 7.63 7.16 7.63 7.71 7.71 7.71 7.71 0.42 0 - - - 8.65 9.12 8.65 9.12 8.65 9.12 8.65 9.12 9.20 9.20 9.20 9.20 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(Tx/Rx) CK clock high period (Tx/Rx) CK clock low period (Tx) CK high to FS (bl) high (Rx) CK high to FS (bl) high (Tx) CK high to FS (bl) low (Rx) CK high to FS (bl) low (Tx) CK high to FS (wl) high (Rx) CK high to FS (wl) high (Tx) CK high to FS (wl) low (Rx) CK high to FS (wl) low (Tx) CK high to STXD valid from high impedance (Tx) CK high to STXD high (Tx) CK high to STXD low (Tx) CK high to STXD high impedance SRXD setup time before (Rx) CK low SRXD hole time after (Rx) CK low
MC9328MX21 Technical Data, Rev. 3.1 52 Freescale Semiconductor
Specifications
Table 34. SSI to SAP Ports Timing Parameters (Continued)
Ref No. 1.8 V 0.1 V Parameter Minimum Maximum Minimum Maximum Synchronous Internal Clock Operation (SAP Ports) 31 32 SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling 23.00 0 - - 21.41 0 - - ns ns 3.0 V 0.3 V Unit
Synchronous External Clock Operation (SAP Ports) 33 34 SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling 1.20 0 - - 0.88 0 - - ns ns
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
Table 35. SSI to SSI1 Ports Timing Parameters
Ref No. 1.8 V 0.1 V Parameter Minimum Maximum Minimum Maximum Internal Clock Operation1 (SSI1 Ports) 1 2 3 4 5 6 7 8 9 10 11a 11b 12 13 14 (Tx/Rx) CK clock period1 (Tx) CK high to FS (bl) high (Rx) CK high to FS (bl) high (Tx) CK high to FS (bl) low (Rx) CK high to FS (bl) low (Tx) CK high to FS (wl) high (Rx) CK high to FS (wl) high (Tx) CK high to FS (wl) low (Rx) CK high to FS (wl) low (Tx) CK high to STXD valid from high impedance (Tx) CK high to STXD high (Tx) CK high to STXD low (Tx) CK high to STXD high impedance SRXD setup time before (Rx) CK low SRXD hold time after (Rx) CK low 90.91 -0.68 -0.96 -0.68 -0.96 -0.68 -0.96 -0.68 -0.96 -1.68 -1.68 -1.68 -1.58 20.41 0 - -0.15 -0.27 -0.15 -0.27 -0.15 -0.27 -0.15 -0.27 -0.36 -0.36 -0.36 -0.31 - - 90.91 -0.68 -0.96 -0.68 -0.96 -0.68 -0.96 -0.68 -0.96 -1.68 -1.68 -1.68 -1.58 20.41 0 - -0.15 -0.27 -0.15 -0.27 -0.15 -0.27 -0.15 -0.27 -0.36 -0.36 -0.36 -0.31 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3.0 V 0.3 V Unit
External Clock Operation (SSI1 Ports) 15 16 17 18 19 (Tx/Rx) CK clock period1 (Tx/Rx) CK clock high period (Tx/Rx) CK clock low period (Tx) CK high to FS (bl) high (Rx) CK high to FS (bl) high 90.91 36.36 36.36 10.22 10.79 - - - 17.63 19.67 90.91 36.36 36.36 8.82 9.39 - - - 16.24 18.28 ns ns ns ns ns
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 53
Specifications
Table 35. SSI to SSI1 Ports Timing Parameters (Continued)
Ref No. 20 21 22 23 24 25 26 27a 27b 28 29 30 1.8 V 0.1 V Parameter Minimum (Tx) CK high to FS (bl) low (Rx) CK high to FS (bl) low (Tx) CK high to FS (wl) high (Rx) CK high to FS (wl) high (Tx) CK high to FS (wl) low (Rx) CK high to FS (wl) low (Tx) CK high to STXD valid from high impedance (Tx) CK high to STXD high (Tx) CK high to STXD low (Tx) CK high to STXD high impedance SRXD setup time before (Rx) CK low SRXD hole time after (Rx) CK low 10.22 10.79 10.22 10.79 10.22 10.79 10.05 10.00 10.00 10.05 0.78 0 Maximum 17.63 19.67 17.63 19.67 17.63 19.67 15.75 15.63 15.63 15.75 - - Minimum 8.82 9.39 8.82 9.39 8.82 9.39 8.66 8.61 8.61 8.66 0.47 0 Maximum 16.24 18.28 16.24 18.28 16.24 18.28 14.36 14.24 14.24 14.36 - - ns ns ns ns ns ns ns ns ns ns ns ns 3.0 V 0.3 V Unit
Synchronous Internal Clock Operation (SSI1 Ports) 31 32 SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling 19.90 0 - - 19.90 0 - - ns ns
Synchronous External Clock Operation (SSI1 Ports) 33 34 SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling 2.59 0 - - 2.28 0 - - ns ns
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
Table 36. SSI to SSI2 Ports Timing Parameters
Ref No. 1.8 V 0.1 V Parameter Minimum Maximum Minimum Maximum Internal Clock Operation1 (SSI2 Ports) 1 2 3 4 5 6 7 8 9 10 (Tx/Rx) CK clock period1 (Tx) CK high to FS (bl) high (Rx) CK high to FS (bl) high (Tx) CK high to FS (bl) low (Rx) CK high to FS (bl) low (Tx) CK high to FS (wl) high (Rx) CK high to FS (wl) high (Tx) CK high to FS (wl) low (Rx) CK high to FS (wl) low (Tx) CK high to STXD valid from high impedance 90.91 0.01 -0.21 0.01 -0.21 0.01 -0.21 0.01 -0.21 0.34 - 0.15 0.05 0.15 0.05 0.15 0.05 0.15 0.05 0.72 90.91 0.01 -0.21 0.01 -0.21 0.01 -0.21 0.01 -0.21 0.34 - 0.15 0.05 0.15 0.05 0.15 0.05 0.15 0.05 0.72 ns ns ns ns ns ns ns ns ns ns 3.0 V 0.3 V Unit
MC9328MX21 Technical Data, Rev. 3.1 54 Freescale Semiconductor
Specifications
Table 36. SSI to SSI2 Ports Timing Parameters (Continued)
Ref No. 11a 11b 12 13 14 1.8 V 0.1 V Parameter Minimum (Tx) CK high to STXD high (Tx) CK high to STXD low (Tx) CK high to STXD high impedance SRXD setup time before (Rx) CK low SRXD hold time after (Rx) CK low 0.34 0.34 0.34 21.50 0 Maximum 0.72 0.72 0.48 - - Minimum 0.34 0.34 0.34 21.50 0 Maximum 0.72 0.72 0.48 - - ns ns ns ns ns 3.0 V 0.3 V Unit
External Clock Operation (SSI2 Ports) 15 16 17 18 19 20 21 22 23 24 25 26 27a 27b 28 29 30 (Tx/Rx) CK clock period1 (Tx/Rx) CK clock high period (Tx/Rx) CK clock low period (Tx) CK high to FS (bl) high (Rx) CK high to FS (bl) high (Tx) CK high to FS (bl) low (Rx) CK high to FS (bl) low (Tx) CK high to FS (wl) high (Rx) CK high to FS (wl) high (Tx) CK high to FS (wl) low (Rx) CK high to FS (wl) low (Tx) CK high to STXD valid from high impedance (Tx) CK high to STXD high (Tx) CK high to STXD low (Tx) CK high to STXD high impedance SRXD setup time before (Rx) CK low SRXD hole time after (Rx) CK low 90.91 36.36 36.36 10.40 11.00 10.40 11.00 10.40 11.00 10.40 11.00 9.59 9.59 9.59 9.59 2.52 0 - - - 17.37 19.70 17.37 19.70 17.37 19.70 17.37 19.70 17.08 17.08 17.08 16.84 - - 90.91 36.36 36.36 8.67 9.28 8.67 9.28 8.67 9.28 8.67 9.28 7.86 7.86 7.86 7.86 2.52 0 - - - 15.88 18.21 15.88 18.21 15.88 18.21 15.88 18.21 15.59 15.59 15.59 15.35 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Synchronous Internal Clock Operation (SSI2 Ports) 31 32 SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling 20.78 0 - - 20.78 0 - - ns ns
Synchronous External Clock Operation (SSI2 Ports) 33 34 SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling 4.42 0 - - 4.42 0 - - ns ns
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 55
Specifications
Table 37. SSI to SSI3 Ports Timing Parameters
Ref No. 1.8 V 0.1 V Parameter Minimum Maximum Minimum Maximum Internal Clock Operation1 (SSI3 Ports) 1 2 3 4 5 6 7 8 9 10 11a 11b 12 13 14 (Tx/Rx) CK clock period1 (Tx) CK high to FS (bl) high (Rx) CK high to FS (bl) high (Tx) CK high to FS (bl) low (Rx) CK high to FS (bl) low (Tx) CK high to FS (wl) high (Rx) CK high to FS (wl) high (Tx) CK high to FS (wl) low (Rx) CK high to FS (wl) low (Tx) CK high to STXD valid from high impedance (Tx) CK high to STXD high (Tx) CK high to STXD low (Tx) CK high to STXD high impedance SRXD setup time before (Rx) CK low SRXD hold time after (Rx) CK low 90.91 -2.09 -2.74 -2.09 -2.74 -2.09 -2.74 -2.09 -2.74 -1.73 -2.87 -2.87 -1.73 22.77 0 - -0.66 -0.84 -0.66 -0.84 -0.66 -0.84 -0.66 -0.84 -0.26 -0.80 -0.80 -0.26 - - 90.91 -2.09 -2.74 -2.09 -2.74 -2.09 -2.74 -2.09 -2.74 -1.73 -2.87 -2.87 -1.73 22.77 0 - -0.66 -0.84 -0.66 -0.84 -0.66 -0.84 -0.66 -0.84 -0.26 -0.80 -0.80 -0.26 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3.0 V 0.3 V Unit
External Clock Operation (SSI3 Ports) 15 16 17 18 19 20 21 22 23 24 25 26 27a 27b (Tx/Rx) CK clock period1 (Tx/Rx) CK clock high period (Tx/Rx) CK clock low period (Tx) CK high to FS (bl) high (Rx) CK high to FS (bl) high (Tx) CK high to FS (bl) low (Rx) CK high to FS (bl) low (Tx) CK high to FS (wl) high (Rx) CK high to FS (wl) high (Tx) CK high to FS (wl) low (Rx) CK high to FS (wl) low (Tx) CK high to STXD valid from high impedance (Tx) CK high to STXD high (Tx) CK high to STXD low 90.91 36.36 36.36 9.62 10.30 9.62 10.30 9.62 10.30 9.62 10.30 9.02 8.48 8.48 - - - 17.10 19.54 17.10 19.54 17.10 19.54 17.10 19.54 16.46 15.32 15.32 90.91 36.36 36.36 7.90 8.58 7.90 8.58 7.90 8.58 7.90 8.58 7.29 6.75 6.75 - - - 15.61 18.05 15.61 18.05 15.61 18.05 15.61 18.05 14.97 13.83 13.83 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MC9328MX21 Technical Data, Rev. 3.1 56 Freescale Semiconductor
Specifications
Table 37. SSI to SSI3 Ports Timing Parameters (Continued)
Ref No. 28 29 30 1.8 V 0.1 V Parameter Minimum (Tx) CK high to STXD high impedance SRXD setup time before (Rx) CK low SRXD hole time after (Rx) CK low 9.02 1.49 0 Maximum 16.46 - - Minimum 7.29 1.49 0 Maximum 14.97 - - ns ns ns 3.0 V 0.3 V Unit
Synchronous Internal Clock Operation (SSI3 Ports) 31 32 SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling 21.99 0 - - 21.99 0 - - ns ns
Synchronous External Clock Operation (SSI3 Ports) 33 34 SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling 3.80 0 - - 3.80 0 - - ns ns
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
3.17
3.17.1
1-Wire Interface Timing
Reset Sequence with Reset Pulse Presence Pulse
To begin any communications with the DS2502, it is required that an initialization procedure be issued. A reset pulse must be generated and then a presence pulse must be detected. The minimum reset pulse length is 480 us. The bus master (one-wire) will generate this pulse, then after the DS2502 detects a rising edge on the one-wire bus, it will wait 15-60 us before it will transmit back a presence pulse. The presence pulse will exist for 60-240 us. The timing diagram for this sequence is shown in Figure 46.
Reset and Presence Pulses
Set RPP 511 us DS2502 waits 15-60us DS2502 Tx "presence pulse" 60-240us AutoClear RPP Control Bit
one-wire BUS 512us 68us One-Wire samples (set PST)
Figure 46. 1-Wire Initialization
The reset pulse begins the initialization sequence and it is initiated when the RPP control register bit is set. When the presence pulse is detected, this bit will be cleared. The presence pulse is used by the bus master to determine if at least one DS2502 is connected. Software will determine if more than one DS2502 exists. The one-wire will sample for the DS2502 presence pulse. The presence pulse is latched in the one-wire
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 57
Specifications
control register PST. When the PST bit is set to a one, it means that a DS2502 is present; if the bit is set to a zero, then no device was found.
3.17.2
Write 0
The Write 0 function simply writes a zero bit to the DS2502. The sequence takes 117 us. The one-wire bus is held low for 100us.
Set WR0 AutoClear WR0
Write 0 Slot 128us 17us 100us one-wire BUS
Figure 47. Write 0 Timing
The Write 0 pulse sequence is initiated when the WR0 control bit register is set. When the write is complete, the WR0 register will be auto cleared.
3.17.3
Write 1/Read Data
The Write 1 and Read timing is identical. The time slot is first driven low. According to the DS2502 documentation, the DS2502 has a delay circuit which is used to synchronize the DS2502 with the bus master (one-wire). This delay circuit is triggered by the falling edge of the data line and is used to decide when the DS2502 should sample the line. In the case of a write 1 or read 1, after a delay, a 1 will be transmitted / received. When a read 0 slot is issued, the delay circuit will hold the data line low to override the 1 generated by the bus master (one-wire). For the Write 1 or Read, the control register WR1/RD is set and auto-cleared when the sequence has been completed. After a Read, the control register RDST bit is set to the value of the read.
Set WR1/RD Auto Clear WR1/R
Write "1" Slot 117us
5us
Figure 48. Write 1 Timing
MC9328MX21 Technical Data, Rev. 3.1 58 Freescale Semiconductor
Specifications
Set WR1/RD Read Timing Auto Clear WR1/RD Set WR1/RD Auto Clear WR1/R
Read "0" Slot 117us 60us
Read "1" Slot 117us
one-wire BUS 5us 13us 5us 13us
One-Wire samples (set RDST)
One-Wire samples (set RDST)
Figure 49. Read Timing
The precision of the generated clock is very important to get a proper behavior of the one-wire module. This module is based on a state machine which undertakes actions at defined times.
Table 38. System Timing Requirements
Times RSTL PST RSTH LOW0 LOWR READ_sample Values (Microsec) 511 68 512 100 5 13 Minimum (Microsec) 480 60 480 60 1 - Maximum (microsec) - 75 - 120 15 15 Absolute Precision 31 7 32 20 4 2 Relative Precision 0.0645 0.1 0.0645 0.2 0.8 0.15
The most stringent constraint is 0.0645 as a relative time imprecision. The time relative precision is directly derived from the frequency of the derivative clock (f): Time relative precision = 1/f -1 = divider/clock (MHz) - 1 The Figure 39 gathers relative time precision for different main clock frequencies.
Table 39. System Clock Requirements
Main Clock Frequency (MHz) Clock divide ratio Generated frequency (MHz) Relative time imprecision 13 13 1 0 16.8 17 0.9882 0.0117 19.44 19 1.023 0.023
This shows that the user should take care of the main clock frequency when using the one-wire module. If the main clock is an exact integer multiple of 1 MHz, then the generated frequency will be exactly 1 MHz.
NOTE:
A main clock frequency below 10 MHz might cause a misbehavior of the module.
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 59
Specifications
3.18
USB On-The-Go
Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous transfers and interrupt transfers. From the perspective of the USB module, the interrupt transfer type is identical to the bulk data transfer mode, and no additional hardware is supplied to support it. This section covers the transfer modes and how they work from the ground up. Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same packet transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved in the form of packets, but because isochronous pipes are given a fixed portion of the USB bandwidth at all times, there is no end-of-transfer.
USB_ON (Output) USB_OE (Output)
tPERIOD 6 3 tTXDP_OEB t OEB_TXDP t TXDM_OEB 4
1
USB_TXDP (Output)
USB_TXDM (Output)
tOEB_TXDM 2 tFEOPT 5
USB_VP (Input) USB_VM (Input)
Figure 50. USB Timing Diagram for Data Transfer to USB Transceiver (TX) Table 40. USB Timing Parameters for Data Transfer to USB Transceiver (TX)
Ref No. 1 2 3 4 5 6 3.0 V 0.3 V Parameter Minimum tOEB_TXDP; USBD_OE active to USBD_TXDP low tOEB_TXDM; USBD_OE active to USBD_TXDM high tTXDP_OEB; USBD_TXDP high to USBD_OE deactivated tTXDM_OEB; USBD_TXDM low to USBD_OE deactivated (includes SE0) tFEOPT; SE0 interval of EOP tPERIOD; Data transfer rate 83.14 81.55 83.54 248.9 160 11.97 Maximum 83.47 81.98 83.8 249.13 175 12.03 ns ns ns ns ns Mb/s Unit
MC9328MX21 Technical Data, Rev. 3.1 60 Freescale Semiconductor
Specifications
USB_ON (Output) USB_OE (Output) USB_TXDP (Output) USB_TXDM (Output)
USB_RXDP (Input) USB_RXDM (Input)
tFEOPR
1
Figure 51. USB Timing Diagram for Data Transfer from USB Transceiver (RX) Table 41. USB Timing Parameters for Data Transfer from USB Transceiver (RX)
3.0 V 0.3 V Ref No. 1 Parameter Minimum tFEOPR; Receiver SE0 interval of EOP 82 Maximum - ns Unit
The USBOTG I2C communication protocol consists of six components: START, Data Source/Recipient, Data Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.
USBG_SDA 5 USBG_SCL 1 2 6 3 4
Figure 52. USB Timing Diagram for Data Transfer from USB Transceiver (I2C) Table 42. USB Timing Parameters for Data Transfer from USB Transceiver (I2C)
1.8 V 0.1 V Ref No. 1 2 3 4 5 6 Parameter Minimum Hold time (repeated) START condition Data hold time Data setup time HIGH period of the SCL clock LOW period of the SCL clock Setup time for STOP condition 188 0 88 500 500 185 Maximum - 188 - - - - ns ns ns ns ns ns Unit
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 61
Specifications
3.19
External Interface Module (EIM)
The External Interface Module (EIM) handles the interface to devices external to the i.MX21, including generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in Figure 53, and Table 43 defines the parameters of signals.
(HCLK) Bus Clock
1a 1b
Address Chip-select
2a 2b
3a
3b
Read (Write) OE (rising edge) OE (falling edge) EB (rising edge) EB (falling edge) LBA (negated falling edge) LBA (negated rising edge)
6a 5a 4a 4b
4c
4d
5b
5c
5d
6b
6a
6c
7a
7b 11 7c 7d
Burst Clock (rising edge) Burst Clock (falling edge) Read Data
9a
8b
8a
9b
Write Data (negated falling)
9a 9c
Write Data (negated rising) DTACK
10a 10a
Figure 53. EIM Bus Timing Diagram
MC9328MX21 Technical Data, Rev. 3.1 62 Freescale Semiconductor
Specifications
Table 43. EIM Bus Timing Parameters
1.8 V 0.1 V Ref No. Parameter Min 1a 1b 2a 2b 3a 3b 4a 4b 4c 4d 5a 5b 5c 5d 6a 6b 6c 7a 7b 7c 7d 8a 8b 9a 9b 9c 10a 11 Clock fall to address valid Clock fall to address invalid Clock fall to chip-select valid Clock fall to chip-select invalid Clock fall to Read (Write) Valid Clock fall to Read (Write) Invalid Clock1 rise to Output Enable Valid 3.97 3.93 3.47 3.39 3.51 3.59 3.62 3.70 3.60 3.69 3.69 4.64 3.52 3.50 3.65 3.65 3.66 3.50 3.49 3.50 3.49 4.54 0.5 4.13 4.10 4.02 2.65 15 Typical 6.02 6.00 5.59 5.09 5.56 5.37 5.49 5.61 5.48 5.62 5.46 5.47 5.06 5.05 5.28 5.67 5.69 5.22 5.19 5.22 5.19 - - 5.86 5.79 5.81 4.63 - Max 9.89 9.86 8.62 8.27 8.79 9.14 8.98 9.26 8.77 9.12 8.71 8.70 8.39 8.27 8.69 9.36 9.48 8.42 8.30 8.39 8.29 - - 9.16 9.15 9.37 8.40 - Min 3.83 3.81 3.30 3.15 3.39 3.36 3.46 3.46 3.44 3.42 3.46 3.46 3.41 3.41 3.30 3.41 3.33 3.26 3.31 3.26 3.31 4.54 0.5 3.95 4.04 4.22 2.64 15 Typical 5.89 5.86 5.09 4.85 5.39 5.20 5.33 5.37 5.30 5.36 5.25 5.25 5.18 5.18 5.23 5.43 5.47 4.99 5.03 4.98 5.02 - - 6.36 6.27 5.29 4.61 - 3.0 V 0.3 V 1.8 V 0.1 V Max 9.79 9.76 8.45 8.03 8.51 8.50 9.02 8.81 8.88 8.60 8.54 8.54 8.36 8.36 8.81 9.13 9.25 8.19 8.17 8.15 8.12 - - 10.31 9.16 9.24 8.41 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Unit
Clock1 rise to Output Enable Invalid Clock1 fall to Output Enable Valid
Clock1 fall to Output Enable Invalid Clock1 rise to Enable Bytes Valid
Clock1 rise to Enable Bytes Invalid Clock1 fall to Enable Bytes Valid
Clock1 fall to Enable Bytes Invalid Clock1 fall to Load Burst Address Valid
Clock1 fall to Load Burst Address Invalid Clock1 rise to Load Burst Address Invalid
Clock1 rise to Burst Clock rise Clock1rise to Burst Clock fall
Clock1 fall to Burst Clock rise Clock1 fall to Burst Clock fall
Read Data setup time Read Data hold time Clock1 rise to Write Data Valid Clock1 fall to Write Data Invalid
Clock1 rise to Write Data Invalid DTACK setup time Burst Clock (BCLK) cycle time
1. Clock refers to the system clock signal, HCLK, generated from the System DPLL
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 63
Specifications
3.19.1
EIM External Bus Timing Diagrams
Note: Signals listed with lower case letters are internal to the device. hclk
The following timing diagrams show the timing of accesses to memory or a peripheral.
hselm_weim_cs[0] htrans hwrite Seq/Nonseq Read V1
haddr hready weim_hrdata weim_hready
Last Valid Data
V1
BCLK A[24:0] CS[0] R/W Read Last Valid Address V1
LBA OE EB (EBC=0) EB (EBC=1)
DATA_IN
V1
Figure 54. WSC = 1, A.HALF/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 64 Freescale Semiconductor
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[0] htrans hwrite haddr Nonseq Write V1
hready hwdata weim_hrdata Last Valid Data Write Data (V1) Last Valid Data Unknown
weim_hready
BCLK A[24:0] CS[0] R/W LBA OE EB Write Last Valid Address V1
D[31:0]
Last Valid Data
Write Data (V1)
Figure 55. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 65
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[0] htrans hwrite haddr
Nonseq Read V1
hready weim_hrdata Last Valid Data V1 Word
weim_hready
BCLK A[24:0] CS[0] R/W LBA OE EB (EBC=0) EB (EBC=1) Read Last Valid Addr Address V1 Address V1 + 2
DATA_IN
1/2 Half Word
2/2 Half Word
Figure 56. WSC = 1, OEA = 1, A.WORD/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 66 Freescale Semiconductor
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[0] htrans hwrite haddr Nonseq Write V1
hready hwdata weim_hrdata Last Valid Data Write Data (V1 Word) Last Valid Data
weim_hready BCLK A[24:0] CS[0] R/W LBA OE EB Last Valid Addr Address V1 Address V1 + 2
Write
D[31:0]
1/2 Half Word
2/2 Half Word
Figure 57. WSC = 1, WEA = 1, WEN = 1, A.WORD/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 67
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk
hselm_weim_cs[3] htrans hwrite haddr hready weim_hrdata Nonseq
Read V1
Last Valid Data
V1 Word
weim_hready BCLK A[24:0] Last Valid Addr CS[3] R/W LBA OE EB (EBC=0) EB (EBC=1) Read Address V1 Address V1 + 2
DATA_IN
1/2 Half Word
2/2 Half Word
Figure 58. WSC = 3, OEA = 2, A.WORD/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 68 Freescale Semiconductor
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[3] htrans hwrite haddr hready hwdata
Last Valid Data Nonseq
Write V1
Write Data (V1 Word) Last Valid Data
weim_hrdata
weim_hready
BCLK A[24:0] Last Valid Addr CS[3] R/W LBA OE Write Address V1 Address V1 + 2
EB
D[31:0]
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 59. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 69
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[2] htrans hwrite haddr
Nonseq
Read V1
hready weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK A[24:0] CS[2] R/W Read Last Valid Addr Address V1 Address V1 + 2
LBA OE EB (EBC=0) EB (EBC=1)
DATA_IN
1/2 Half Word
2/2 Half Word
Figure 60. WSC = 3, OEA = 4, A.WORD/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 70 Freescale Semiconductor
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[2] htrans hwrite haddr
Nonseq
Write V1
hready hwdata weim_hrdata weim_hready BCLK A[24:0] CS[2] R/W LBA OE Last Valid Addr Address V1 Address V1 + 2
Last Valid Data
Write Data (V1 Word) Last Valid Data
Write
EB
D[31:0]
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 61. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 71
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[2] htrans
Nonseq
hwrite haddr hready weim_hrdata
Read V1
Last Valid Data
V1 Word
weim_hready BCLK A[24:0] CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) Read Last Valid Addr Address V1 Address V1 + 2
DATA_IN
1/2 Half Word
2/2 Half Word
Figure 62. WSC = 3, OEN = 2, A.WORD/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 72 Freescale Semiconductor
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[2] htrans hwrite haddr
Nonseq
Read V1
hready weim_hrdata Last Valid Data V1 Word
weim_hready
BCLK A[24:0] CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) Read Last Valid Addr Address V1 Address V1 + 2
DATA_IN
1/2 Half Word
2/2 Half Word
Figure 63. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 73
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[2] htrans hwrite haddr hready hwdata weim_hrdata
Last Valid Data
Nonseq
Write V1
Write Data (V1 Word)
Unknown
Last Valid Data
weim_hready
BCLK A[24:0] CS[2] R/W LBA OE EB Last Valid Addr Address V1 Address V1 + 2
Write
D[31:0]
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 64. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 74 Freescale Semiconductor
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[2] htrans hwrite haddr hready hwdata weim_hrdata
Last Valid Data Nonseq
Write V1
Write Data (V1 Word) Last Valid Data
Unknown
weim_hready
BCLK A[24:0] CS[2] R/W LBA OE EB Last Valid Addr Address V1 Address V1 + 2
Write
D[31:0]
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 65. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 75
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[2] htrans hwrite haddr hready hwdata weim_hrdata weim_hready
Nonseq Nonseq
Read V1
Write V8
Last Valid Data Last Valid Data
Write Data Read Data
BCLK A[24:0] CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) Read Write Last Valid Addr Address V1 Address V8
DATA_IN D[31:0]
Read Data
Last Valid Data
Write Data
Figure 66. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 76 Freescale Semiconductor
Specifications
Note: Signals listed with lower case letters are internal to the device. Read hclk hselm_weim_cs[2] htrans hwrite haddr Idle Write
Nonseq
Nonseq
Read V1
Write V8
hready hwdata weim_hrdata
Last Valid Data
Write Data
Last Valid Data
Read Data
weim_hready
BCLK A[24:0] CS[2] R/W LBA OE EB (EBC=0) Read Write Last Valid Addr Address V1 Address V8
EB (EBC=1)
DATA_IN D[31:0]
Read Data Last Valid Data Write Data
Figure 67. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 77
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk
hselm_weim_cs[4] htrans hwrite haddr hready hwdata weim_hrdata
Last Valid Data
Nonseq
Write V1
Write Data (Word) Last Valid Data
weim_hready
BCLK A[24:0] CS[3:0] R/W Last Valid Addr Address V1 Address V1 + 2
Write
LBA OE
EB
D[31:0]
Last Valid Data
Write Data (1/2 Half Word)
Write Data (2/2 Half Word)
Figure 68. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 78 Freescale Semiconductor
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[4] htrans hwrite haddr
Nonseq Nonseq
Read V1
Write V8
hready hwdata weim_hrdata weim_hready Last Valid Data Last Valid Data Write Data Read Data
BCLK A[24:0] CS[4] R/W LBA OE EB (EBC=0) EB (EBC=1) Read Write Last Valid Addr Address V1 Address V8
DATA_IN D[31:0]
Read Data
Last Valid Data
Write Data
Figure 69. WSC = 3, CSA = 1, A.HALF/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 79
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[4] htrans hwrite haddr
Nonseq
Idle
Seq
Read V1
Read V2
hready weim_hrdata weim_hready Last Valid Data Read Data (V1) Read Data (V2)
BCLK A[24:0]
Last Valid Addr
Address V1 CNC
Address V2
CS[4] R/W LBA Read
OE EB (EBC=0) EB (EBC=1) DATA_IN
Read Data (V1) Read Data (V2)
Figure 70. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 80 Freescale Semiconductor
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[4] htrans hwrite haddr hready hwdata weim_hrdata
Nonseq
Idle
Nonseq
Read V1
Write V8
Last Valid Data Last Valid Data
Write Data Read Data
weim_hready
BCLK A[24:0]
Last Valid Addr
Address V1 CNC
Address V8
CS[4] R/W LBA OE EB (EBC=0) EB (EBC=1)
Read
Write
DATA_IN D[31:0]
Read Data Last Valid Data Write Data
Figure 71. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 81
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hrdata weim_hready BCLK A[24:0]
Nonseq Nonseq
Idle
Read V1
Read V5
Last Valid Addr
Address V1
Address V5
CS[2] R/W LBA Read
OE EB (EBC=0) EB (EBC=1)
ECB DATA_IN
V5 Word V6 Word
V1 Word V2 Word
Figure 72. WSC = 3, SYNC = 1, A.HALF/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 82 Freescale Semiconductor
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) Read Last Valid Data V1 Word V2 Word V3 Word V4 Word
Nonseq
Seq
Seq
Seq
Idle
Read V1
Read V2
Read V3
Read V4
Address V1
ECB DATA_IN V1 Word V2 Word V3 Word V4 Word
Figure 73. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 83
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hrdata Last Valid Data V1 Word V2 Word
Nonseq
Seq
Idle
Read V1
Read V2
weim_hready BCLK A[24:0] CS[2] R/W LBA OE Read
Last Valid Addr
Address V1
Address V2
EB (EBC=0) EB (EBC=1)
ECB DATA_IN V1 1/2 V1 2/2 V2 1/2 V2 2/2
Figure 74. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 84 Freescale Semiconductor
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hrdata Last Valid Data V1 Word V2 Word
Non seq
Seq
Idle
Read V1
Read V2
weim_hready BCLK A[24:0] CS[2] Read
Last Valid Addr
Address V1
R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Figure 75. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 85
Specifications
Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hrdata Last Valid Data V1 Word V2 Word
Non seq
Seq
Idle
Read V1
Read V2
weim_hready BCLK A[24:0] CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN V1 1/2 V1 2/2 V2 1/2 V2 2/2
Last Valid Addr
Address V1
Read
Figure 76. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF
MC9328MX21 Technical Data, Rev. 3.1 86 Freescale Semiconductor
Specifications
3.20
DTACK Mode Memory Access Timing Diagrams
When enabled, the DTACK input signal is used to externally terminate a data transfer. For DTACK enabled operations, a bus time-out monitor generates a bus error when an external bus cycle is not terminated by the DTACK input signal after 1024 HCLK clock cycles have elapsed, where HCLK is the internal system clock driven from the PLL module. For a 133 MHz HCLK setting, this time equates to 7.7 s. Refer to the Section 3.5, "DPLL Timing Specifications" for more information on how to generate different HCLK frequencies. There are two modes of operation for the DTACK input signal: rising edge detection or level sensitive detection with a programmable insensitivity time. DTACK is only used during external asynchronous data transfers, thus the SYNC bit in the chip select control registers must be cleared. During edge detection mode, the EIM will terminate an external data transfer following the detection of the DTACK signal's rising edge, so long as it occurs within the 1024 HCLK cycle time. Edge detection mode is used for devices that follow the PCMCIA standard. Note that DTACK rising edge detection mode can only be used for CS[5] operations. To configure CS[5] for DTACK rising edge detection, the following bits must be programmed in the Chip Select 5 Control Register and EIM Configuration Register:
* * WSC bit field set to 0x3F and CSA (or CSN) set to 1 or greater in the Chip Select 5 Control Register AGE bit set in the EIM Configuration Register
Other bits such as DSZ, OEA, OEN, and so on, may be set according to system and timing requirements of the external device. The requirement of setting CSA or CSN is required to allow the EIM to wait for the rising edge of DTACK during back-to-back external transfers, such as during DMA transfers or an internal 32-bit access through an external 16-bit data port. During level sensitive detection, the EIM will first hold off sampling the DTACK signal for at least 2 HCLK cycles, and up to 5 HCLK cycles as programmed by the DCT bits in the Chip Select Control Register. After this insensitivity time, the EIM will sample DTACK and if it detects that DTACK is logic high, it will continue the data transfer at the programmed number of wait states. However, if the EIM detects that DTACK is logic low, it will wait until DTACK goes to logic high to continue the access, so long as this occurs within the 1024 HCLK cycle time. If at anytime during an external data transfer DTACK goes to logic low, the EIM will wait until DTACK returns to logic high to resume the data transfer. Level detection is often used for asynchronous devices such graphic controller chips. Level detection may be used with any chip select except CS[4] as it is multiplexed with the DTACK signal. To configure a chip select for DTACK level sensitive detection, the following bits must be programmed in the Chip Select Control Register and EIM Configuration Register:
* * * EW bit set, WSC set to > 1, and CSN set to < 3 in the Chip Select Control Register BCD/DCT set to desired "insensitivity time" in the Chip Select Control Register. The "insensitivity time" is dictated by the external device's timing requirements. AGE bit cleared in the EIM Configuration Register
Other bits such as DSZ, OEA, OEN, and so on, may be set according to system and timing requirements of the external device. The waveforms in the following section provide examples of the DTACK signal operation.
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 87
Specifications
3.20.1
DTACK Example Waveforms: Internal ARM AHB Word Accesses to Word-Width (32-bit) Memory
Internal Signal HCLK BCLK ADDR CS[5] Read
Last Valid Addr
V1
RW LBA
OE EB (EBC=0)
EB (EBC=1) DTACK
DATA_IN
V1 Data
Figure 77. DTACK Edge Triggered Read Access, WSC=3F, OEA=8, OEN=5, AGE=1.
MC9328MX21 Technical Data, Rev. 3.1 88 Freescale Semiconductor
Specifications
HCLK Internal Signal BCLK ADDR Address V1 V1+4 V1+8
Last Valid Addr
CS[0] Read
RW LBA
OE EB (EBC=0)
EB (EBC=1) DCT DTACK
DATA_IN
V1 Word
V1+4 Word
V1+8 Word
Figure 78. DTACK Level Sensitive Sequential Read Accesses, WSC=2, EW=1, DCT=1, AGE=0 (Example of DTACK Remaining High)
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 89
Specifications
HCLK
Internal Signal
BCLK ADDR Last Valid Addr CS[0] Address V1 V1+4 V1+8
RWA Write
RWN
RW
LBA
OE
EB
DCT DTACK DATA_OUT V1 Word V1+4 Word V1+8
Figure 79. DTACK Level Sensitive Sequential Write Accesses, WSC=2, EW=1, RWA=1, RWN=1, DCT=1, AGE=0 (Example of DTACK Asserting)
MC9328MX21 Technical Data, Rev. 3.1 90 Freescale Semiconductor
Specifications
3.21
I2C Module
The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.
SDA 3 5 SCL 1 2 2 6
4
Figure 80. Definition of Bus Timing for I C Table 44. I2C Bus Timing Parameters
Ref No. 1.8 V 0.1 V Parameter Minimum SCL Clock Frequency 1 2 3 4 5 6 Hold time (repeated) START condition Data hold time Data setup time HIGH period of the SCL clock LOW period of the SCL clock Setup time for STOP condition 0 114.8 0 3.1 69.7 336.4 110.5 Maximum 100 - 69.7 - - - - Minimum 0 111.1 0 1.76 68.3 335.1 111.1 Maximum 100 - 72.3 - - - - kHz ns ns ns ns ns ns 3.0 V 0.3 V Unit
3.22
CMOS Sensor Interface
The CSI module consists of a control register to configure the interface timing, a control register for statistic data generation, a status register, interface logic, a 32 x 32 image data receive FIFO, and a 16 x 32 statistic data FIFO.
3.22.1
Gated Clock Mode
Figure 81 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the CSI is programmed to received data on the positive edge. Figure 82 shows the timing diagram when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative edge. The parameters for the timing diagrams are listed in Table 45. The formula for calculating the pixel clock rise and fall time is located in Section 3.22.3, "Calculation of Pixel Clock Rise/ Fall Time."
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 91
Specifications
1
VSYNC
7
HSYNC
2
5
6
PIXCLK
DATA[7:0]
Valid Data
3 4
Valid Data
Valid Data
Figure 81. Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge
1
VSYNC
7
HSYNC
2
5
6
PIXCLK
DATA[7:0]
Valid Data
3 4
Valid Data
Valid Data
Figure 82. Sensor Output Data on Pixel Clock Rising Edge CSI Latches Data on Pixel Clock Falling Edge Table 45. Gated Clock Mode Timing Parameters
Number 1 2 3 4 5 6 7 Parameter csi_vsync to csi_hsync csi_hsync to csi_pixclk csi_d setup time csi_d hold time csi_pixclk high time csi_pixclk low time csi_pixclk frequency Minimum 9 * THCLK 3 1 1 THCLK THCLK 0 Maximum - Unit ns ns ns ns ns ns MHz
(TP/2) - 3
- - - - HCLK / 2
HCLK = AHB System Clock, THCLK = Period for HCLK, TP = Period of CSI_PIXCLK
MC9328MX21 Technical Data, Rev. 3.1 92 Freescale Semiconductor
Specifications
The limitation on pixel clock rise time/fall time is not specified. It should be calculated from the hold time and setup time based on the following assumptions: Rising-edge latch data max rise time allowed = (positive duty cycle - hold time) max fall time allowed = (negative duty cycle - setup time) In most of case, duty cycle is 50 / 50, therefore max rise time = (period / 2 - hold time) max fall time = (period / 2 - setup time) For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns. positive duty cycle = 10 / 2 = 5ns max rise time allowed = 5 - 1 = 4ns negative duty cycle = 10 / 2 = 5ns max fall time allowed = 5 - 1 = 4ns Falling-edge latch data max fall time allowed = (negative duty cycle - hold time) max rise time allowed = (positive duty cycle - setup time)
3.22.2
Non-Gated Clock Mode
Figure 83 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the CSI is programmed to received data on the positive edge. Figure 84 shows the timing diagram when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative edge. The parameters for the timing diagrams are listed in Table 46. The formula for calculating the pixel clock rise and fall time is located in Section 3.22.3, "Calculation of Pixel Clock Rise/ Fall Time."
1
VSYNC
4
6 5
PIXCLK
DATA[7:0]
Valid Data
2 3
Valid Data
Valid Data
Figure 83. Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 93
Specifications
1 6 5 4
VSYNC
PIXCLK
DATA[7:0]
Valid Data 2 3
Valid Data
Valid Data
Figure 84. Sensor Output Data on Pixel Clock Rising Edge CSI Latches Data on Pixel Clock Falling Edge Table 46. Non-Gated Clock Mode Parameters1
Number 1 2 3 4 5 6 Parameter csi_vsync to csi_pixclk csi_d setup time csi_d hold time csi_pixclk high time csi_pixclk low time csi_pixclk frequency Minimum 9 * THCLK 1 1 THCLK THCLK 0 Maximum - - - - - HCLK / 2 Unit ns ns ns ns ns MHz
1. HCLK = AHB System Clock, THCLK = Period of HCLK
3.22.3
Calculation of Pixel Clock Rise/Fall Time
The limitation on pixel clock rise time/fall time is not specified. It should be calculated from the hold time and setup time based on the following assumptions: Rising-edge latch data
* * * * max rise time allowed = (positive duty cycle - hold time) max fall time allowed = (negative duty cycle - setup time) max rise time = (period / 2 - hold time) max fall time = (period / 2 - setup time) positive duty cycle = 10 / 2 = 5ns max rise time allowed = 5 - 1 = 4ns negative duty cycle = 10 / 2 = 5ns max fall time allowed = 5 - 1 = 4ns
In most of case, duty cycle is 50 / 50, therefore:
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
Falling-edge latch data
* * max fall time allowed = (negative duty cycle - hold time) max rise time allowed = (positive duty cycle - setup time)
MC9328MX21 Technical Data, Rev. 3.1 94 Freescale Semiconductor
4
1 A B C D E F G H J K L M N P R T U V W LD9 LD7 LD1 LD2 LD8
Pin Assignment and Package Information
Table 47. i.MX21 Pin Assignment
2 LD12 LD5 LD3 LD0 LD4 D31 D29 D27 A18 A17 A15_ NFIO10 A13_ NFIO8 A12 A10 A8 A6 EB1 EB0 A2 3 LD14 LD11 LD6 LD13 LD15 4 REV LD16 LD10 CLS SPL_ SPR 5 HSYNC PS LD17 QVDD 6 OE_ ACD 7 SD2_D2 8 CSI_ D0 SD2_ CMD CSI_ D1 SD2_ CLK 9 CSI_ PIXCLK CSI_ D4 CSI_ MCLK CSI_ D2 10 CSI_ VSYNC CSI_D6 CSI_ HSYNC CSI_D7 11 12 13 USBG_ FS USBG_ TXDM USBG_ RXDM USBG_ ON 14 TOUT SAP_ FS TIN USBG_ RXDP 15 SAP_ TXDAT SSI1_ FS SSI1_ TXDAT SAP_ RXDAT 16 SSI1_ CLK SSI2_ FS SSI3_ RXDAT SSI1_ RXDAT SAP_ CLK CSPI1_ SS1 NVDD6 NVDD1 NVSS6 NVSS5 CSI_D3 CSI_D5 NVDD4 QVDDX QVDD NVSS3 USB_ BYP CSPI1_ SCLK KP_ ROW5 UART1_ RXD QVSS QVSS NVSS1 USBH_ ON CSPI1_ RDY KP_ ROW2 TDO NFIO2 NFIO7 NVSS1 USBG_ SDA USBH1_ TXDP CSPI1_ MOSI QVDD NFWP NFRB NVDD1 USBG_ TXDP USBG_ OE TEST_ WB0 QVSS UART1_ TXD EXT_ 48M NVDD1 KP_ ROW1 TEST_ WB4 17 SSI2_ RXDAT SSI3_ TXDAT SSI3_ CLK SSI2_ CLK CSPI2_ MISO CSPI1_ MISO KP_ ROW3 TEST_ WB2 18 SSI2_TXDAT I2C_DATA I2C_CLK CSPI2_SS0 CSPI1_SS2 KP_ROW0 UART2_CTS TEST_WB3 KP_COL0 KP_COL4 UART3_CTS UART1_RTS SD1_D1 TDI NVSS2 CLKMODE1 BOOT3 VDDA QVDD 19 SSI3_ FS CSPI2_ SS2 CSPI2_ SS1 CSPI2_ SCLK CSPI2_ MOSI CSPI1_ SS0 KP_ ROW4 PWMO TEST_ WB1 KP_ COL2 UART3_ TXD UART1_ CTS RTCK
Freescale Semiconductor MC9328MX21 Technical Data, Rev. 3.1 95
USBH1_ USBH1_ OE FS USB_ PWR USB_ OC USBG_ SCL USBH1_ RXDM
CON SD2_D0 TRAST VSYNC SD2_D3 QVSS SD2_D1
USBH1_ USBH1_ TXDM RXDP
A24_ NFIO14 A22_ NFIO12 A20 A19 A16 A14_ NFIO9 D19 A11 A9 A7 A5 D11 A4 A3
A25_ LSCLK NFIO15 A23_ NFIO13 A21_ NFIO11 D25 D23 D21 D20 D17 D15 D13 EB3 EB2 D9 D7 D30 D28 D26 D24 D22 D18 D16 D14 D12 D10 OE D8 A1 CS3 CS4 CS5 CS2 CS1 D6 D5 A0 BCLK ECB CS0 D4 MA11 D3 RW D2 RAS MA10 D1 D0 CAS PC_ PWRON JTAG_ CTRL SDCLK NFIO5 PF16 SDWE SDCKE1 NFIO3 NFIO4 CLKO NFIO0 NFWE NFIO1 NFIO6 NFRE RESET_ IN NFALE QVSS QVDD NFCE NFCLE RESET_ OUT QVSS
NVDD1 NVDD5 NVSS1 NVSS1 NVSS4 NVDD3
UART2_ KP_COL1 RTS KP_ COL3 UART2_ TXD UART2_ RXD SD1_ D0 SD1_ D2 SD1_ CLK BOOT1 POR BOOT0 EXTAL 26M KP_COL5 UART3_ RTS UART3_ RXD TCK SD1_ CMD EXT_ 266M SD1_D3 BOOT2 OSC26M_ TEST XTAL26M
NVDD2 NVDD3 LBA
NVSS3 SDCKE0
Pin Assignment and Package Information
TMS TRST CLK MODE0 XTAL32K EXTAL 32K QVSS
Pin Assignment and Package Information
4.1
MAPBGA Package Dimensions
Figure 85 illustrates the MAPBGA 14 mm x 14 mm x 1.41 mm package, which has 0.65 mm ball pitch.
Figure 85. i.MX21 MAPBGA Mechanical Drawing
MC9328MX21 Technical Data, Rev. 3.1 96 Freescale Semiconductor
Pin Assignment and Package Information
4.2
MAPBGA Package Dimensions
Figure 86 illustrates the MAPBGA 17 mm x 17 mm x 1.45 mm package, which has 0.8 mm spacing between the pads.
Figure 86. i.MX21 MAPBGA Mechanical Drawing
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 97
5
Document Revision History
Table 48. Document Revision History
Location Page 10 Description of Change Removed table referenceing Tri-StateTM signal timing.
Table 48 provides the document changes for the MC9328MX21 Rev. 3.1.
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Document Number: MC9328MX21 Rev. 3.1 07/2006

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